📄 main.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 939] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -omain.o --depend=main.d --device=DARMSTM --apcs=interwork -O3 -I.\ -IC:\KeilARM\ARM\INC\ST\STM32F10x --omf_browse=main.crf main.c]
THUMB
AREA ||i.GPIO_Configuration||, CODE, READONLY, ALIGN=2
GPIO_Configuration PROC
000000 b508 PUSH {r3,lr}
000002 200f MOVS r0,#0xf
000004 f8ad0000 STRH r0,[sp,#0]
000008 2018 MOVS r0,#0x18
00000a f88d0003 STRB r0,[sp,#3]
00000e 2003 MOVS r0,#3
000010 f88d0002 STRB r0,[sp,#2]
000014 4669 MOV r1,sp
000016 4802 LDR r0,|L1.32|
000018 f7fffffe BL GPIO_Init
00001c bd08 POP {r3,pc}
ENDP
00001e 0000 DCW 0x0000
|L1.32|
000020 40010800 DCD 0x40010800
AREA ||i.NVIC_Configuration||, CODE, READONLY, ALIGN=1
NVIC_Configuration PROC
000000 b508 PUSH {r3,lr}
000002 2100 MOVS r1,#0
000004 f04f6000 MOV r0,#0x8000000
000008 f7fffffe BL NVIC_SetVectorTable
00000c 201c MOVS r0,#0x1c
00000e f88d0000 STRB r0,[sp,#0]
000012 2000 MOVS r0,#0
000014 f88d0001 STRB r0,[sp,#1]
000018 f88d0002 STRB r0,[sp,#2]
00001c 2001 MOVS r0,#1
00001e f88d0003 STRB r0,[sp,#3]
000022 4668 MOV r0,sp
000024 f7fffffe BL NVIC_Init
000028 bd08 POP {r3,pc}
ENDP
AREA ||i.RCC_Configuration||, CODE, READONLY, ALIGN=2
RCC_Configuration PROC
;;;103 void RCC_Configuration(void)
;;;104 {
000000 b510 PUSH {r4,lr}
;;;105 /* RCC system reset(for debug purpose) */
;;;106 RCC_DeInit();
000002 f7fffffe BL RCC_DeInit
;;;107
;;;108 /* Enable HSE */
;;;109 RCC_HSEConfig(RCC_HSE_ON);
000006 f44f3480 MOV r4,#0x10000
00000a 4620 MOV r0,r4
00000c f7fffffe BL RCC_HSEConfig
;;;110
;;;111 /* Wait till HSE is ready */
;;;112 HSEStartUpStatus = RCC_WaitForHSEStartUp();
000010 f7fffffe BL RCC_WaitForHSEStartUp
000014 4919 LDR r1,|L3.124|
000016 7008 STRB r0,[r1,#0] ; HSEStartUpStatus
;;;113
;;;114 if(HSEStartUpStatus == SUCCESS)
000018 b2c0 UXTB r0,r0
00001a 2801 CMP r0,#1
00001c d124 BNE |L3.104|
;;;115 {
;;;116 /* HCLK = SYSCLK */
;;;117 RCC_HCLKConfig(RCC_SYSCLK_Div1);
00001e 2000 MOVS r0,#0
000020 f7fffffe BL RCC_HCLKConfig
;;;118
;;;119 /* PCLK2 = HCLK */
;;;120 RCC_PCLK2Config(RCC_HCLK_Div1);
000024 2000 MOVS r0,#0
000026 f7fffffe BL RCC_PCLK2Config
;;;121
;;;122 /* PCLK1 = HCLK/4 */
;;;123 RCC_PCLK1Config(RCC_HCLK_Div4);
00002a f44f60a0 MOV r0,#0x500
00002e f7fffffe BL RCC_PCLK1Config
;;;124
;;;125 /* Flash 2 wait state */
;;;126 FLASH_SetLatency(FLASH_Latency_2);
000032 2002 MOVS r0,#2
000034 f7fffffe BL FLASH_SetLatency
;;;127 /* Enable Prefetch Buffer */
;;;128 FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
000038 2010 MOVS r0,#0x10
00003a f7fffffe BL FLASH_PrefetchBufferCmd
;;;129
;;;130 /* PLLCLK = 8MHz * 9 = 72 MHz */
;;;131 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
00003e f44f11e0 MOV r1,#0x1c0000
000042 4620 MOV r0,r4
000044 f7fffffe BL RCC_PLLConfig
;;;132
;;;133 /* Enable PLL */
;;;134 RCC_PLLCmd(ENABLE);
000048 2001 MOVS r0,#1
00004a f7fffffe BL RCC_PLLCmd
|L3.78|
;;;135
;;;136 /* Wait till PLL is ready */
;;;137 while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00004e 2039 MOVS r0,#0x39
000050 f7fffffe BL RCC_GetFlagStatus
000054 2800 CMP r0,#0
000056 d0fa BEQ |L3.78|
;;;138 {
;;;139 }
;;;140
;;;141 /* Select PLL as system clock source */
;;;142 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
000058 2002 MOVS r0,#2
00005a f7fffffe BL RCC_SYSCLKConfig
;;;143
;;;144 /* Wait till PLL is used as system clock source */
;;;145 while(RCC_GetSYSCLKSource() != 0x08)
00005e bf00 NOP
|L3.96|
000060 f7fffffe BL RCC_GetSYSCLKSource
000064 2808 CMP r0,#8
000066 d1fb BNE |L3.96|
|L3.104|
;;;146 {
;;;147 }
;;;148 }
;;;149
;;;150 /* TIM2 clock enable */
;;;151 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
000068 2101 MOVS r1,#1
00006a 4608 MOV r0,r1
00006c f7fffffe BL RCC_APB1PeriphClockCmd
;;;152
;;;153 /* GPIOA clock enable */
;;;154 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
000070 2101 MOVS r1,#1
000072 e8bd4010 POP {r4,lr}
000076 2004 MOVS r0,#4
000078 f7ffbffe B.W RCC_APB2PeriphClockCmd
;;;155 }
;;;156
ENDP
|L3.124|
00007c 00000000 DCD ||.data||
AREA ||i.main||, CODE, READONLY, ALIGN=2
main PROC
;;;37 int main(void)
;;;38 {
000000 e92d41f0 PUSH {r4-r8,lr}
;;;39 #ifdef DEBUG
;;;40 debug();
;;;41 #endif
;;;42
;;;43 /* System Clocks Configuration */
;;;44 RCC_Configuration();
000004 f7fffffe BL RCC_Configuration
;;;45
;;;46 /* NVIC Configuration */
;;;47 NVIC_Configuration();
000008 f7fffffe BL NVIC_Configuration
;;;48
;;;49 /* GPIO Configuration */
;;;50 GPIO_Configuration();
00000c f7fffffe BL GPIO_Configuration
;;;51
;;;52 /* ---------------------------------------------------------------
;;;53 TIM2 Configuration: Output Compare Toggle Mode:
;;;54 TIM2CLK = 36 MHz, Prescaler = 0x2, TIM2 counter clock = 12 MHz
;;;55 CC1 update rate = TIM2 counter clock / CCR1_Val = 366.2 Hz
;;;56 CC2 update rate = TIM2 counter clock / CCR2_Val = 732.4 Hz
;;;57 CC3 update rate = TIM2 counter clock / CCR3_Val = 1464.8 Hz
;;;58 CC4 update rate = TIM2 counter clock / CCR4_Val = 2929.6 Hz
;;;59 --------------------------------------------------------------- */
;;;60
;;;61 /* Time base configuration */
;;;62 TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
000010 481e LDR r0,|L4.140|
000012 f64f71ff MOV r1,#0xffff
000016 8081 STRH r1,[r0,#4] ; TIM_TimeBaseStructure
;;;63 TIM_TimeBaseStructure.TIM_Prescaler = 0x02;
000018 2602 MOVS r6,#2
00001a 8006 STRH r6,[r0,#0] ; TIM_TimeBaseStructure
;;;64 TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
00001c 2100 MOVS r1,#0
00001e 80c1 STRH r1,[r0,#6] ; TIM_TimeBaseStructure
;;;65 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
000020 8041 STRH r1,[r0,#2] ; TIM_TimeBaseStructure
;;;66
;;;67 TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
000022 4601 MOV r1,r0
000024 0777 LSLS r7,r6,#29
000026 4638 MOV r0,r7
000028 f7fffffe BL TIM_TimeBaseInit
;;;68
;;;69 /* Output Compare Toggle Mode configuration: Channel1 */
;;;70 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
00002c 4c17 LDR r4,|L4.140|
00002e 2030 MOVS r0,#0x30
000030 340a ADDS r4,r4,#0xa
000032 8020 STRH r0,[r4,#0] ; TIM_OCInitStructure
;;;71 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
000034 2501 MOVS r5,#1
000036 8065 STRH r5,[r4,#2] ; TIM_OCInitStructure
;;;72 TIM_OCInitStructure.TIM_Pulse = 2047;
000038 f24070ff MOV r0,#0x7ff
00003c 80e0 STRH r0,[r4,#6] ; TIM_OCInitStructure
;;;73 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00003e 8126 STRH r6,[r4,#8] ; TIM_OCInitStructure
;;;74 TIM_OC1Init(TIM2, &TIM_OCInitStructure);
000040 4621 MOV r1,r4
000042 4638 MOV r0,r7
000044 f7fffffe BL TIM_OC1Init
;;;75 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
000048 8065 STRH r5,[r4,#2] ; TIM_OCInitStructure
;;;76 TIM_OCInitStructure.TIM_Pulse = 1023;
00004a f24030ff MOV r0,#0x3ff
00004e 80e0 STRH r0,[r4,#6] ; TIM_OCInitStructure
;;;77 TIM_OC2Init(TIM2, &TIM_OCInitStructure);
000050 4621 MOV r1,r4
000052 4638 MOV r0,r7
000054 f7fffffe BL TIM_OC2Init
;;;78 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
000058 8065 STRH r5,[r4,#2] ; TIM_OCInitStructure
;;;79 TIM_OCInitStructure.TIM_Pulse = 511;
00005a f24010ff MOV r0,#0x1ff
00005e 80e0 STRH r0,[r4,#6] ; TIM_OCInitStructure
;;;80 TIM_OC3Init(TIM2, &TIM_OCInitStructure);
000060 4621 MOV r1,r4
000062 4638 MOV r0,r7
000064 f7fffffe BL TIM_OC3Init
;;;81 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
000068 8065 STRH r5,[r4,#2] ; TIM_OCInitStructure
;;;82 TIM_OCInitStructure.TIM_Pulse = 255;
00006a 20ff MOVS r0,#0xff
00006c 80e0 STRH r0,[r4,#6] ; TIM_OCInitStructure
;;;83 TIM_OC4Init(TIM2, &TIM_OCInitStructure);
00006e 4621 MOV r1,r4
000070 4638 MOV r0,r7
000072 f7fffffe BL TIM_OC4Init
;;;84
;;;85 /* TIM enable counter */
;;;86 TIM_Cmd(TIM2, ENABLE);
000076 2101 MOVS r1,#1
000078 4638 MOV r0,r7
00007a f7fffffe BL TIM_Cmd
;;;87
;;;88 /* TIM IT enable */
;;;89 TIM_ITConfig(TIM2, TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4, ENABLE);
00007e 2201 MOVS r2,#1
000080 211e MOVS r1,#0x1e
000082 4638 MOV r0,r7
000084 f7fffffe BL TIM_ITConfig
|L4.136|
;;;90
;;;91 while(1)
000088 e7fe B |L4.136|
;;;92 {
;;;93 }
;;;94 }
;;;95
ENDP
00008a 0000 DCW 0x0000
|L4.140|
00008c 00000000 DCD ||.bss||
AREA ||.data||, DATA, ALIGN=0
HSEStartUpStatus
000000 00 DCB 0x00
AREA ||.bss||, DATA, NOINIT, ALIGN=1
TIM_TimeBaseStructure
% 10
TIM_OCInitStructure
% 16
AREA |area_number.7|, DATA, ALIGN=1
EXPORTAS |area_number.7|, ||.data||
CCR1_Val
000000 8000 DCW 0x8000
AREA |area_number.8|, DATA, ALIGN=1
EXPORTAS |area_number.8|, ||.data||
CCR2_Val
000000 4000 DCW 0x4000
AREA |area_number.9|, DATA, ALIGN=1
EXPORTAS |area_number.9|, ||.data||
CCR3_Val
000000 2000 DCW 0x2000
AREA |area_number.10|, DATA, ALIGN=1
EXPORTAS |area_number.10|, ||.data||
CCR4_Val
000000 1000 DCW 0x1000
__ARM_use_no_argv EQU 0
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