opb_interproc_int_if_v2_1_0.mpd

FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

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## opb_interproc_int_if_v2_1_0.mpd
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## Microprocessor Peripheral Definition file
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BEGIN opb_interproc_int_if

OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL

BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = INT_PORT0, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = INT_PORT1, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = INT_PORT2, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = INT_PORT3, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF

PARAMETER C_OPB_AWIDTH = 32, DT = integer, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = integer, BUS = SOPB
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0xF, BUS = SOPB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB

PORT OPB_Clk = "", DIR = IN, SIGIS = CLK, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = IN, BUS = SOPB

PORT OPB_ABus = OPB_ABus, DIR = IN, VEC = [0:C_OPB_AWIDTH - 1], BUS = SOPB
PORT OPB_BE   = OPB_BE, DIR = IN, VEC = [0:C_OPB_DWIDTH/8 - 1], BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = IN, VEC = [0:C_OPB_DWIDTH - 1], BUS = SOPB
PORT OPB_RNW  = OPB_RNW, DIR = IN, BUS = SOPB
PORT OPB_select = OPB_select, DIR = IN, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = IN, BUS = SOPB

PORT InterProcIntIf_DBus = Sl_DBus, DIR = OUT, VEC = [0:C_OPB_DWIDTH - 1], BUS = SOPB
PORT InterProcIntIf_errAck = Sl_errAck, DIR = OUT, BUS = SOPB
PORT InterProcIntIf_retry = Sl_retry, DIR = OUT, BUS = SOPB
PORT InterProcIntIf_toutSup = Sl_toutSup, DIR = OUT, BUS = SOPB
PORT InterProcIntIf_xferAck = Sl_xferAck, DIR = OUT, BUS = SOPB

PORT Interrupt = "", DIR = OUT, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = HIGH

PORT RCV_IntReq0 = SND_IntReq, DIR = IN, BUS = INT_PORT0
PORT SND_IntReq0 = RCV_IntReq, DIR = OUT, BUS = INT_PORT0

PORT RCV_IntReq1 = SND_IntReq, DIR = IN, BUS = INT_PORT1
PORT SND_IntReq1 = RCV_IntReq, DIR = OUT, BUS = INT_PORT1

PORT RCV_IntReq2 = SND_IntReq, DIR = IN, BUS = INT_PORT2
PORT SND_IntReq2 = RCV_IntReq, DIR = OUT, BUS = INT_PORT2

PORT RCV_IntReq3 = SND_IntReq, DIR = IN, BUS = INT_PORT3
PORT SND_IntReq3 = RCV_IntReq, DIR = OUT, BUS = INT_PORT3

END