📄 opb_spin_lock_if.vhd
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elsif (s_select = '1' and OPB_RNW = '0' and LOCKED = '1') then NEXT_STATE <= RELEASE_LOCK; else NEXT_STATE <= IDLE; end if; when ACQUIRE_LOCK => if (SpinLock_Ack = '1') then NEXT_STATE <= IDLE; end if; when RELEASE_LOCK => if (SpinLock_Ack = '1') then NEXT_STATE <= IDLE; end if; when others => NEXT_STATE <= CURRENT_STATE; end case; end if; end process; --Chip Enable process (OPB_Clk, OPB_Rst) begin -- process if OPB_Rst = '1' then -- asynchronous reset (active low) SpinLock_CE0Tsk <= '0'; SpinLock_CE1Tsk <= '0'; SpinLock_CE2Tsk <= '0'; SpinLock_CE3Tsk <= '0'; SpinLock_CE0Obj <= '0'; SpinLock_CE1Obj <= '0'; SpinLock_CE2Obj <= '0'; SpinLock_CE3Obj <= '0'; elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge if (NEXT_STATE = ACQUIRE_LOCK or NEXT_STATE = RELEASE_LOCK) then SpinLock_CE0Tsk <= s_select and SEL(TSK0) and not SpinLock_Ack; SpinLock_CE1Tsk <= s_select and SEL(TSK1); SpinLock_CE2Tsk <= s_select and SEL(TSK2); SpinLock_CE3Tsk <= s_select and SEL(TSK3); SpinLock_CE0Obj <= s_select and SEL(OBJ0); SpinLock_CE1Obj <= s_select and SEL(OBJ1); SpinLock_CE2Obj <= s_select and SEL(OBJ2); SpinLock_CE3Obj <= s_select and SEL(OBJ3); else SpinLock_CE0Tsk <= '0'; SpinLock_CE1Tsk <= '0'; SpinLock_CE2Tsk <= '0'; SpinLock_CE3Tsk <= '0'; SpinLock_CE0Obj <= '0'; SpinLock_CE1Obj <= '0'; SpinLock_CE2Obj <= '0'; SpinLock_CE3Obj <= '0'; end if; end if; end process; --Read Not Write-- SpinLock_RNW <= OPB_RNW; SpinLock_Tsk0_RNW <= OPB_RNW; SpinLock_Tsk1_RNW <= OPB_RNW; SpinLock_Tsk2_RNW <= OPB_RNW; SpinLock_Tsk3_RNW <= OPB_RNW; SpinLock_Obj0_RNW <= OPB_RNW; SpinLock_Obj1_RNW <= OPB_RNW; SpinLock_Obj2_RNW <= OPB_RNW; SpinLock_Obj3_RNW <= OPB_RNW; --Set TSK, OBJ Register process (OPB_Clk, OPB_Rst) begin -- process if OPB_Rst = '1' then -- asynchronous reset (active low) TSK_REG0 <= (others => '0'); TSK_REG1 <= (others => '0'); TSK_REG2 <= (others => '0'); TSK_REG3 <= (others => '0'); OBJ_REG0 <= (others => '0'); OBJ_REG1 <= (others => '0'); OBJ_REG2 <= (others => '0'); OBJ_REG3 <= (others => '0'); elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge if (SpinLock_Ack = '1' and SpinLock_TestSetBit = '0' and CURRENT_STATE = ACQUIRE_LOCK) then case OPB_ABus(27 to 29) is when TSK_ADDR0 => TSK_REG0(LOCKBIT) <= '1'; when TSK_ADDR1 => TSK_REG1(LOCKBIT) <= '1'; when TSK_ADDR2 => TSK_REG2(LOCKBIT) <= '1'; when TSK_ADDR3 => TSK_REG3(LOCKBIT) <= '1'; when OBJ_ADDR0 => OBJ_REG0(LOCKBIT) <= '1'; when OBJ_ADDR1 => OBJ_REG1(LOCKBIT) <= '1'; when OBJ_ADDR2 => OBJ_REG2(LOCKBIT) <= '1'; when OBJ_ADDR3 => OBJ_REG3(LOCKBIT) <= '1'; when others => null; end case; elsif (SpinLock_Ack = '1' and CURRENT_STATE = RELEASE_LOCK) then case OPB_ABus(27 to 29) is when TSK_ADDR0 => TSK_REG0(LOCKBIT) <= '0'; when TSK_ADDR1 => TSK_REG1(LOCKBIT) <= '0'; when TSK_ADDR2 => TSK_REG2(LOCKBIT) <= '0'; when TSK_ADDR3 => TSK_REG3(LOCKBIT) <= '0'; when OBJ_ADDR0 => OBJ_REG0(LOCKBIT) <= '0'; when OBJ_ADDR1 => OBJ_REG1(LOCKBIT) <= '0'; when OBJ_ADDR2 => OBJ_REG2(LOCKBIT) <= '0'; when OBJ_ADDR3 => OBJ_REG3(LOCKBIT) <= '0'; when others => null; end case; end if; end if; end process; process (OPB_Clk, OPB_Rst) begin -- process if OPB_Rst = '1' then -- asynchronous reset (active low) SpinLockIf_DBus(31) <= '0'; elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge case CURRENT_STATE is when IDLE => if (s_select = '1' and OPB_RNW = '1' and LOCKED = '1') then SpinLockIf_DBus(31) <= '1'; else SpinLockIf_DBus(31) <= '0'; end if; when ACQUIRE_LOCK => if (SpinLock_Ack = '1') then SpinLockIf_DBus(31) <= SpinLock_TestSetBit; end if; when others => SpinLockIf_DBus(31) <= '0'; end case; end if; end process; --To Opb SpinLockIf_toutSup <= s_select; SpinLockIf_errAck <= '0'; SpinLockIf_retry <= '0'; process (OPB_Clk, OPB_Rst) begin -- process if OPB_Rst = '1' then -- asynchronous reset (active low) i_xfer_ack <= '0'; elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge i_xfer_ack <= xfer_ack; end if; end process; SpinLockIf_xferAck <= s_select and xfer_ack and not i_xfer_ack; process (OPB_Clk, OPB_Rst) begin -- process if OPB_Rst = '1' then -- asynchronous reset (active low) xfer_ack <= '0'; elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge case CURRENT_STATE is when IDLE => if (s_select = '1' and OPB_RNW = '1' and LOCKED = '1') then xfer_ack <= '1'; elsif (s_select = '1' and OPB_RNW = '0' and LOCKED = '0') then xfer_ack <= '1'; else xfer_ack <= '0'; end if; when ACQUIRE_LOCK => if (SpinLock_Ack = '1') then xfer_ack <= '1'; else xfer_ack <= '0'; end if; when RELEASE_LOCK => if (SpinLock_Ack = '1') then xfer_ack <= '1'; else xfer_ack <= '0'; end if; when others => xfer_ack <= '0'; end case; end if; end process; --SpinLockIf_DBus SpinLockIf_DBus(0 to 30) <= (others => '0'); --toutSup-- SpinLockIf_toutSup <= '0';-- process (OPB_Clk, OPB_Rst)-- variable timer_count : integer;-- begin -- process-- if OPB_Rst = '1' then -- asynchronous reset (active low)-- timer_count := 0;-- SpinLockIf_toutSup <= '0';-- elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge-- if (s_select = '1') then-- if (timer_count /= 14) then-- timer_count := timer_count + 1;-- else-- timer_count := 0;-- SpinLockIf_toutSup <= '1';-- end if;-- else-- timer_count := 0;-- SpinLockIf_toutSup <= '0';-- end if;-- end if;-- end process; -- process (OPB_Clk, OPB_Rst)-- variable timer_count : std_logic_vector(3 downto 0);-- begin -- process-- if OPB_Rst = '1' then -- asynchronous reset (active low)-- timer_count := (others => '0');-- SpinLockIf_toutSup <= '0';-- elsif OPB_Clk'event and OPB_Clk = '1' then -- rising clock edge-- if (s_select = '1') then-- if (timer_count /= X"D") then-- timer_count := timer_count + '1';-- else-- timer_count := (others => '0');-- SpinLockIf_toutSup <= '1';-- end if;-- else-- timer_count := (others => '0');-- SpinLockIf_toutSup <= '0';-- end if;-- end if;-- end process;end RTL;
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