opb_spin_lock_if_v2_1_0.mpd

FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

#####################################################################
##
## opb_spin_lock_if_v2_1_0.mpd
##
## Microprocessor Peripheral Definition file
##
#####################################################################


BEGIN opb_spin_lock_if

OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL

BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE
BUS_INTERFACE BUS = TSK0_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = TSK1_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = TSK2_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = TSK3_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = OBJ0_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = OBJ1_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = OBJ2_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
BUS_INTERFACE BUS = OBJ3_PORT, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF


PARAMETER C_OPB_AWIDTH = 32, DT = integer, BUS = SOPB
PARAMETER C_OPB_DWIDTH = 32, DT = integer, BUS = SOPB
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x40, BUS = SOPB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SOPB


PORT OPB_Clk = "", DIR = IN, SIGIS = CLK, BUS = SOPB
PORT OPB_Rst = OPB_Rst, DIR = IN, BUS = SOPB

PORT OPB_ABus = OPB_ABus, DIR = IN, VEC = [0:C_OPB_AWIDTH - 1], BUS = SOPB
PORT OPB_BE   = OPB_BE, DIR = IN, VEC = [0:C_OPB_DWIDTH/8 - 1], BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = IN, VEC = [0:C_OPB_DWIDTH - 1], BUS = SOPB
PORT OPB_RNW  = OPB_RNW, DIR = IN, BUS = SOPB
PORT OPB_select = OPB_select, DIR = IN, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = IN, BUS = SOPB

PORT SpinLockIf_DBus = Sl_DBus, DIR = OUT, VEC = [0:C_OPB_DWIDTH - 1], BUS = SOPB
PORT SpinLockIf_errAck = Sl_errAck, DIR = OUT, BUS = SOPB
PORT SpinLockIf_retry = Sl_retry, DIR = OUT, BUS = SOPB
PORT SpinLockIf_toutSup = Sl_toutSup, DIR = OUT, BUS = SOPB
PORT SpinLockIf_xferAck = Sl_xferAck, DIR = OUT, BUS = SOPB

# to spin_lock
#PORT SpinLock_RNW = SpinLock_RNW, DIR = OUT, BUS = TSK0_PORT:TSK1_PORT:TSK2_PORT:TSK3_PORT:OBJ0_PORT:OBJ1_PORT:OBJ2_PORT:OBJ3_PORT
PORT SpinLock_Tsk0_RNW = SpinLock_RNW, DIR = OUT, BUS = TSK0_PORT
PORT SpinLock_Tsk1_RNW = SpinLock_RNW, DIR = OUT, BUS = TSK1_PORT
PORT SpinLock_Tsk2_RNW = SpinLock_RNW, DIR = OUT, BUS = TSK2_PORT
PORT SpinLock_Tsk3_RNW = SpinLock_RNW, DIR = OUT, BUS = TSK3_PORT
PORT SpinLock_Obj0_RNW = SpinLock_RNW, DIR = OUT, BUS = OBJ0_PORT
PORT SpinLock_Obj1_RNW = SpinLock_RNW, DIR = OUT, BUS = OBJ1_PORT
PORT SpinLock_Obj2_RNW = SpinLock_RNW, DIR = OUT, BUS = OBJ2_PORT
PORT SpinLock_Obj3_RNW = SpinLock_RNW, DIR = OUT, BUS = OBJ3_PORT
PORT SpinLock_Tsk0_Ack = SpinLock_Ack, DIR = IN, BUS = TSK0_PORT
PORT SpinLock_Tsk1_Ack = SpinLock_Ack, DIR = IN, BUS = TSK1_PORT
PORT SpinLock_Tsk2_Ack = SpinLock_Ack, DIR = IN, BUS = TSK2_PORT
PORT SpinLock_Tsk3_Ack = SpinLock_Ack, DIR = IN, BUS = TSK3_PORT
PORT SpinLock_Obj0_Ack = SpinLock_Ack, DIR = IN, BUS = OBJ0_PORT
PORT SpinLock_Obj1_Ack = SpinLock_Ack, DIR = IN, BUS = OBJ1_PORT
PORT SpinLock_Obj2_Ack = SpinLock_Ack, DIR = IN, BUS = OBJ2_PORT
PORT SpinLock_Obj3_Ack = SpinLock_Ack, DIR = IN, BUS = OBJ3_PORT
PORT SpinLock_Tsk0_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = TSK0_PORT
PORT SpinLock_Tsk1_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = TSK1_PORT
PORT SpinLock_Tsk2_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = TSK2_PORT
PORT SpinLock_Tsk3_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = TSK3_PORT
PORT SpinLock_Obj0_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = OBJ0_PORT
PORT SpinLock_Obj1_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = OBJ1_PORT
PORT SpinLock_Obj2_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = OBJ2_PORT
PORT SpinLock_Obj3_TestSetBit = SpinLock_TestSetBit, DIR = IN, BUS = OBJ3_PORT
PORT SpinLock_CE0Tsk = SpinLock_CE, DIR = OUT, BUS = TSK0_PORT
PORT SpinLock_CE1Tsk = SpinLock_CE, DIR = OUT, BUS = TSK1_PORT
PORT SpinLock_CE2Tsk = SpinLock_CE, DIR = OUT, BUS = TSK2_PORT
PORT SpinLock_CE3Tsk = SpinLock_CE, DIR = OUT, BUS = TSK3_PORT
PORT SpinLock_CE0Obj = SpinLock_CE, DIR = OUT, BUS = OBJ0_PORT
PORT SpinLock_CE1Obj = SpinLock_CE, DIR = OUT, BUS = OBJ1_PORT
PORT SpinLock_CE2Obj = SpinLock_CE, DIR = OUT, BUS = OBJ2_PORT
PORT SpinLock_CE3Obj = SpinLock_CE, DIR = OUT, BUS = OBJ3_PORT
END