class.ptf

FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>proc_int 1.0</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2006.02.12.22:58:02";
               }
               TEXT 
               {
                  title = "Class name: proc_int";
               }
               TEXT 
               {
                  title = "Class version: 1.0";
               }
               TEXT 
               {
                  title = "Component name: proc_int";
               }
               TEXT 
               {
                  title = "Component Group: Other";
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "5.10";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
      }
      SW_FILES 
      {
      }
      built_on = "2006.02.12.22:58:02";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE proc_int.vhd
         {
            file_mod = "Sun Feb 12 22:55:17 JST 2006";
            quartus_map_start = "Sun Feb 12 22:56:21 JST 2006";
            quartus_map_finished = "Sun Feb 12 22:56:26 JST 2006";
            #found 1 valid modules
            WRAPPER proc_int
            {
               CLASS proc_int
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           filepath = "C:/Home/altera/sopcbuilder/proc_int.vhd";
                        }
                     }
                     top_module_name = "proc_int";
                     emit_system_h = "0";
                     LIBRARIES 
                     {
                        library = "ieee.std_logic_1164.all";
                        library = "std.standard.all";
                     }
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "proc_int";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT chipselect
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "chipselect";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT address
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "address";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT write
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "write";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT writedata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "writedata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT read
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "read";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT readdata
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "readdata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT byteenable
                           {
                              width = "4";
                              width_expression = "";
                              direction = "input";
                              type = "byteenable";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT waitrequest
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "waitrequest";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT irq
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "irq";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     PORT_WIRING 
                     {
                        PORT clk
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "clk";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                        PORT reset_n
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "reset_n";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "proc_int";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
               }
            }
         }
      }
   }
   ASSOCIATED_FILES 
   {
      Add_Program = "the_wizard_ui";
      Edit_Program = "the_wizard_ui";
      Generator_Program = "cb_generator.pl";
   }
}