📄 class.ptf
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#
# This class.ptf file built by Component Editor
# 2006.02.12.22:58:02
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS proc_int
{
CB_GENERATOR
{
HDL_FILES
{
FILE
{
use_in_simulation = "1";
use_in_synthesis = "1";
filepath = "hdl/proc_int.vhd";
}
}
top_module_name = "proc_int.vhd:proc_int";
emit_system_h = "0";
LIBRARIES
{
library = "ieee.std_logic_1164.all";
library = "std.standard.all";
}
}
MODULE_DEFAULTS global_signals
{
class = "proc_int";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Has_Clock = "1";
Top_Level_Ports_Are_Enumerated = "1";
}
COMPONENT_BUILDER
{
GLS_SETTINGS
{
}
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT reset_n
{
width = "1";
width_expression = "";
direction = "input";
type = "reset_n";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
hdl_parameters
{
}
}
SIMULATION
{
DISPLAY
{
}
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Group = "1";
Has_Clock = "0";
Address_Width = "1";
Address_Alignment = "native";
Data_Width = "32";
Has_Base_Address = "1";
Has_IRQ = "1";
Setup_Time = "0";
Hold_Time = "0";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Read_Latency = "0";
Maximum_Pending_Read_Transactions = "0";
Active_CS_Through_Read_Latency = "0";
Is_Printable_Device = "0";
Is_Memory_Device = "0";
Is_Readable = "1";
Is_Writable = "1";
Minimum_Uninterrupted_Run_Length = "1";
}
COMPONENT_BUILDER
{
AVS_SETTINGS
{
Setup_Value = "0";
Read_Wait_Value = "1";
Write_Wait_Value = "1";
Hold_Value = "0";
Timing_Units = "cycles";
Read_Latency_Value = "0";
Minimum_Arbitration_Shares = "1";
Active_CS_Through_Read_Latency = "0";
Max_Pending_Read_Transactions_Value = "1";
Address_Alignment = "native";
Is_Printable_Device = "0";
interface_name = "Avalon Slave";
external_wait = "1";
Is_Memory_Device = "0";
}
}
PORT_WIRING
{
PORT chipselect
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT address
{
width = "1";
width_expression = "";
direction = "input";
type = "address";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT write
{
width = "1";
width_expression = "";
direction = "input";
type = "write";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT writedata
{
width = "32";
width_expression = "";
direction = "input";
type = "writedata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT read
{
width = "1";
width_expression = "";
direction = "input";
type = "read";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT readdata
{
width = "32";
width_expression = "";
direction = "output";
type = "readdata";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT byteenable
{
width = "4";
width_expression = "";
direction = "input";
type = "byteenable";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT waitrequest
{
width = "1";
width_expression = "";
direction = "output";
type = "waitrequest";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
PORT irq
{
width = "1";
width_expression = "";
direction = "output";
type = "irq";
is_shared = "0";
vhdl_record_name = "";
vhdl_record_type = "";
}
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "proc_int";
technology = "Other";
}
WIZARD_UI the_wizard_ui
{
title = "proc_int - {{ $MOD }}";
CONTEXT
{
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