📄 std_2s60.ptf
字号:
{
PORT rxd
{
direction = "input";
width = "1";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
{
component_pin = "J19.3";
pin_assignment = "H7";
}
originally_shared = "0";
}
PORT txd
{
direction = "output";
width = "1";
Is_Enabled = "1";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
{
component_pin = "J19.2";
pin_assignment = "J5";
}
originally_shared = "0";
}
PORT cts_n
{
direction = "input";
width = "1";
Is_Enabled = "0";
}
PORT rts_n
{
direction = "output";
width = "1";
Is_Enabled = "0";
}
}
}
MODULE sysid
{
class = "altera_avalon_sysid";
class_version = "5.11";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "1";
Data_Width = "32";
Base_Address = "0x07110080";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Read_Latency = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
View
{
Settings_Summary = "System ID (at last Generate):<br> <b>115ED2F5</b> (unique ID tag) <br> <b>43EF549D</b> (timestamp: Mon Feb 13, 2006 @0:30 AM)";
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "sys_clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
value0 = "3165772932u";
value1 = "1077149968u";
MAKE
{
TARGET verifysysid
{
verifysysid
{
All_Depends_On = "0";
Command = "nios2-download $(JTAG_CABLE) --sidp=0x07110080 --id=291427061 --timestamp=1139758237";
Target_File = "dummy_verifysysid_file";
Is_Phony = "1";
}
}
}
id = "291427061u";
timestamp = "1139758237u";
}
}
MODULE pll
{
class = "altera_avalon_pll";
class_version = "5.11";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/pll.vhd, __PROJECT_DIRECTORY__/altpllpll.vhd";
Synthesis_Only_Files = "";
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Default_Module_Name = "pll";
Clock_Source = "clk";
Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
Settings_Summary = " Avalon PLL: <br> input clock configured: <b>clk</b> ";
}
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "0";
Read_Wait_States = "1";
Write_Wait_States = "0";
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Requires_Internal_Clock_Promotion = "Yes";
Is_Clock_Source = "1";
Base_Address = "0x071100A0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "0";
}
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT c0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT c1
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT read
{
Is_Enabled = "1";
direction = "input";
type = "read";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT resetrequest
{
Is_Enabled = "1";
direction = "output";
type = "resetrequest";
width = "1";
}
PORT write
{
Is_Enabled = "1";
direction = "input";
type = "write";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
locked = "None";
areset = "None";
pllena = "None";
pfdena = "None";
Config_Done = "1";
UI_CONTROL
{
areset_port_exist = "0";
pllena_port_exist = "0";
pfdena_port_exist = "0";
locked_port_exist = "0";
}
ALTPLL_PORTS
{
PORT c0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT c1
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT inclk0
{
Is_Enabled = "1";
direction = "input";
type = "in_clk";
width = "1";
}
}
CLOCK_INFO
{
CLOCK inclk0
{
clock_freq = "50000000";
clock_unit = "MHz";
type = "in_clk";
}
NUMBER_OF_INPUT_CLOCKS = "1";
NUMBER_OF_OUTPUT_CLOCKS = "2";
RECONFIG_ENABLED = "0";
USED_OUTPUT_CLOCKS
{
INDEX_0 = "0";
INDEX_1 = "1";
}
}
CLOCK_SOURCES
{
CLOCK c0
{
DIVIDE_BY = "1";
DUTY_CYCLE = "50";
MULTIPLY_BY = "1";
PHASE_SHIFT = "0";
clk_index = "0";
clock_freq = "50000000";
clock_unit = "MHz";
type = "out_clk";
}
CLOCK c1
{
DIVIDE_BY = "1";
DUTY_CYCLE = "50";
MULTIPLY_BY = "1";
PHASE_SHIFT = "-3500";
clk_index = "1";
clock_freq = "50000000";
clock_unit = "MHz";
type = "out_clk";
}
}
CNX_INFO
{
CONSTANT
{
NUMERIC
{
CLK0_DIVIDE_BY = "1";
CLK0_DUTY_CYCLE = "50";
CLK0_MULTIPLY_BY = "1";
CLK1_DIVIDE_BY = "1";
CLK1_DUTY_CYCLE = "50";
CLK1_MULTIPLY_BY = "1";
INCLK0_INPUT_FREQUENCY = "20000";
SPREAD_FREQUENCY = "0";
}
STRING
{
BANDWIDTH_TYPE = "AUTO";
CLK0_PHASE_SHIFT = "0";
CLK1_PHASE_SHIFT = "-3500";
COMPENSATE_CLOCK = "CLK0";
INTENDED_DEVICE_FAMILY = "Stratix II";
LPM_TYPE = "altpll";
OPERATION_MODE = "NORMAL";
PLL_TYPE = "ENHANCED";
}
}
GEN_FILE
{
TYPE_NORMAL
{
FALSE
{
name2 = ".cmp";
name1 = ".inc";
name4 = "_inst.v";
name7 = "_wave*.jpg";
}
TRUE
{
name6 = "_waveforms.html";
name0 = ".v";
name3 = ".bsf";
name5 = "_bb.v";
}
}
}
LIBRARY = "altera_mf altera_mf.altera_mf_components.all";
PRIVATE
{
NUMERIC
{
DIV_FACTOR0 = "1";
DIV_FACTOR1 = "1";
GLOCK_COUNTER_EDIT = "1048575";
LVDS_MODE_DATA_RATE_DIRTY = "0";
MULT_FACTOR0 = "1";
MULT_FACTOR1 = "1";
PLL_AUTOPLL_CHECK = "0";
PLL_ENHPLL_CHECK = "1";
PLL_FASTPLL_CHECK = "0";
PLL_LVDS_PLL_CHECK = "0";
SWITCHOVER_COUNT_EDIT = "1";
PLL_TARGET_HARCOPY_CHECK = "0";
}
STRING
{
ACTIVECLK_CHECK = "0";
BANDWIDTH = "1.000";
BANDWIDTH_FEATURE_ENABLED = "1";
BANDWIDTH_FREQ_UNIT = "MHz";
BANDWIDTH_PRESET = "Low";
BANDWIDTH_USE_AUTO = "1";
BANDWIDTH_USE_CUSTOM = "0";
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -