std_2s60.ptf

FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
         contents_info = "SIMDIR/ext_ram_lane0.dat 1124882109 SIMDIR/ext_ram_lane3.dat 1124882109 SIMDIR/ext_ram_lane2.dat 1124882109 SIMDIR/ext_ram.dat 1124882109 SIMDIR/ext_ram_lane1.dat 1124882109 ";
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "32";
               is_shared = "1";
               direction = "inout";
               type = "data";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U35-U36.D0,U35-U36.D1,U35-U36.D2,U35-U36.D3,U35-U36.D4,U35-U36.D5,U35-U36.D6,U35-U36.D7,U35-U36.D8,U35-U36.D9,U35-U36.D10,U35-U36.D11,U35-U36.D12,U35-U36.D13,U35-U36.D14,U35-U36.D15,U35-U36.D16,U35-U36.D17,U35-U36.D18,U35-U36.D19,U35-U36.D20,U35-U36.D21,U35-U36.D22,U35-U36.D23,U35-U36.D24,U35-U36.D25,U35-U36.D26,U35-U36.D27,U35-U36.D28,U35-U36.D29,U35-U36.D30,U35-U36.D31";
                  pin_assignment = "E16,G15,E19,D20,G19,D19,E20,F20,T4,T5,U3,U4,T8,T9,V3,V4,U5,U6,T6,T7,U7,U8,V5,V6,V7,V8,W5,W6,W7,W8,AA5,AA6";
               }
               originally_shared = "1";
            }
            PORT address
            {
               width = "18";
               is_shared = "1";
               direction = "input";
               type = "address";
               lsb = "2";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U35-U36.A0,U35-U36.A1,U35-U36.A2,U35-U36.A3,U35-U36.A4,U35-U36.A5,U35-U36.A6,U35-U36.A7,U35-U36.A8,U35-U36.A9,U35-U36.A10,U35-U36.A11,U35-U36.A12,U35-U36.A13,U35-U36.A14,U35-U36.A15,U35-U36.A16,U35-U36.A17";
                  pin_assignment = "U1,U2,V1,V2,W1,W2,Y1,Y2,AA1,AA2,AB1,AB2,W3,W4,Y3,Y4,AA3,AA4";
               }
               originally_shared = "1";
            }
            PORT read_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "read_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U35-U36.OE_n";
                  pin_assignment = "J22";
               }
               originally_shared = "0";
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U35-U36.WE_n";
                  pin_assignment = "J21";
               }
               originally_shared = "0";
            }
            PORT be_n
            {
               width = "4";
               is_shared = "0";
               direction = "input";
               type = "byteenable_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U35-U36.BE_n0,U35-U36.BE_n1,U35-U36.BE_n2,U35-U36.BE_n3";
                  pin_assignment = "K20,K19,K22,K21";
               }
               originally_shared = "0";
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U35-U36.CS_n";
                  pin_assignment = "J19";
               }
               originally_shared = "0";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Data_Width = "32";
            Address_Width = "18";
            Has_IRQ = "0";
            Read_Wait_States = "0ns";
            Write_Wait_States = "0ns";
            Hold_Time = "half";
            Base_Address = "0x07000000";
            Address_Span = "1048576";
            MASTERED_BY ext_ram_bus/tristate_master
            {
               priority = "1";
            }
            Setup_Time = "0";
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            Is_Base_Locked = "0";
            Address_Group = "0";
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Make_Memory_Model = "1";
         Default_Module_Name = "sram";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "sys_clk";
         Top_Level_Ports_Are_Enumerated = "1";
      }
   }
   MODULE lan91c111
   {
      class = "altera_avalon_lan91c111";
      class_version = "5.1";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         CONSTANTS 
         {
            CONSTANT LAN91C111_REGISTERS_OFFSET
            {
               value = "0x0300";
               comment = "offset 0 or 0x300, depending on address bus wiring";
            }
            CONSTANT LAN91C111_DATA_BUS_WIDTH
            {
               value = "32";
               comment = "width 16 or 32, depending on data bus wiring";
            }
         }
         Is_Ethernet_Mac = "1";
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "0";
         Wire_Test_Bench_Values = "1";
         Is_Enabled = "1";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "sys_clk";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Instantiate_In_System_Module = "0";
            Is_Enabled = "1";
            Is_Bus_Master = "0";
            Bus_Type = "avalon_tristate";
            Uses_Tri_State_Data_Bus = "1";
            Address_Alignment = "native";
            Address_Width = "14";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "175ns";
            Write_Wait_States = "175ns";
            Setup_Time = "10ns";
            Hold_Time = "5ns";
            Is_Memory_Device = "0";
            Date_Modified = "2002.03.19.10:51:51";
            Base_Address = "0x07100000";
            Tri_State_Data_Bus = "--unknown--";
            MASTERED_BY ext_ram_bus/tristate_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "6";
            }
            Address_Group = "0";
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "6";
            }
         }
         PORT_WIRING 
         {
            PORT irq
            {
               direction = "output";
               width = "1";
               type = "irq";
               test_bench_value = "0";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U4.29";
                  pin_assignment = "AD11";
               }
               originally_shared = "0";
            }
            PORT byteenablen
            {
               is_shared = "0";
               direction = "input";
               width = "4";
               type = "byteenable_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U4.94,U4.95,U4.96,U4.97";
                  pin_assignment = "AD8,AF9,Y11,W12";
               }
               originally_shared = "0";
            }
            PORT address
            {
               is_shared = "1";
               direction = "input";
               width = "14";
               type = "address";
               lsb = "2";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U4.79,U4.80,U4.81,U4.82,U4.83,U4.84,U4.85,U4.86,U4.87,U4.88,U4.89,U4.90,U4.91,U4.92";
                  pin_assignment = "U1,U2,V1,V2,W1,W2,Y1,Y2,AA1,AA2,AB1,AB2,W3,W4";
               }
               originally_shared = "1";
            }
            PORT data
            {
               is_shared = "1";
               direction = "inout";
               width = "32";
               type = "data";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U4.107,U4.106,U4.105,U4.104,U4.102,U4.101,U4.100,U4.99,U4.76,U4.75,U4.74,U4.73,U4.71,U4.70,U4.69,U4.68,U4.66,U4.65,U4.64,U4.63,U4.61,U4.60,U4.59,U4.58,U4.56,U4.55,U4.54,U4.53,U4.51,U4.50,U4.49,U4.48";
                  pin_assignment = "E16,G15,E19,D20,G19,D19,E20,F20,T4,T5,U3,U4,T8,T9,V3,V4,U5,U6,T6,T7,U7,U8,V5,V6,V7,V8,W5,W6,W7,W8,AA5,AA6";
               }
               originally_shared = "1";
            }
            PORT iow_n
            {
               direction = "input";
               width = "1";
               type = "write_n";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U4.32";
                  pin_assignment = "AE11";
               }
               originally_shared = "0";
            }
            PORT ior_n
            {
               direction = "input";
               width = "1";
               type = "read_n";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U4.31";
                  pin_assignment = "AC10";
               }
               originally_shared = "0";
            }
            PORT reset_n
            {
               direction = "input";
               width = "1";
               type = "reset_n";
               Is_Enabled = "0";
            }
            PORT reset
            {
               direction = "input";
               width = "1";
               type = "reset";
               is_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "use_quartus_pin_assignment";
                  pin_assignment = "";
               }
               originally_shared = "0";
            }
            PORT ardy
            {
               direction = "output";
               width = "1";
               type = "inhibitrequest_n";
               Is_Enabled = "0";
            }
         }
      }
   }
   MODULE button_pio
   {
      class = "altera_avalon_pio";
      class_version = "5.11";
      HDL_INFO 
      {
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.vhd";
         Precompiled_Simulation_Library_Files = "";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            direction = "input";
            width = "4";
            test_bench_value = "15";
            Is_Enabled = "1";
            is_shared = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               pin_assignment = "W24,W23,Y24,Y23";
               component_pin = "SW0-SW3.SW0,SW0-SW3.SW1,SW0-SW3.SW2,SW0-SW3.SW3";
            }
            originally_shared = "0";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "4";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "4";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "2";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "4";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "4";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "1";
            Address_Width = "2";
            Data_Width = "4";
            Base_Address = "0x07110000";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu_1/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "5";
            }
            Address_Group = "0";
            MASTERED_BY cpu_2/data_master
            {
               priority = "1";
            }