std_2s60.ptf

FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

SYSTEM std_2s60
{
   System_Wizard_Version = "5.10";
   System_Wizard_Build = "213";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "STRATIXII";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "0";
      do_build_sim = "0";
      hdl_language = "vhdl";
      view_master_columns = "1";
      view_master_priorities = "0";
      board_class = "altera_nios_dev_board_stratix_2s60";
      name_column_width = "438";
      desc_column_width = "437";
      bustype_column_width = "0";
      base_column_width = "75";
      end_column_width = "74";
      view_frame_window = "67:28:1535:903";
      do_log_history = "0";
      device_family_id = "STRATIXII";
      CLOCKS 
      {
         CLOCK sys_clk
         {
            Is_Clock_Source = "0";
            frequency = "50000000";
            source = "pll_c0";
            display_name = "sys_clk";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK pll_c1
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c1 from pll";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK pll_c0
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from pll";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK sdram_clk_out
         {
            frequency = "50000000";
            source = "pll_c1";
            Is_Clock_Source = "0";
            display_name = "sdram_clk_out";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK clk
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
      }
      clock_column_width = "64";
      BOARD_INFO 
      {
         CONFIGURATION factory
         {
            length = "";
            menu_position = "2";
            offset = "0xC00000";
            reference_designator = "U5";
         }
         CONFIGURATION user
         {
            length = "";
            menu_position = "1";
            offset = "0x800000";
            reference_designator = "U5";
         }
         JTAG_device_index = "1";
         REFDES U5
         {
            base = "0x01000000";
         }
         altera_avalon_cfi_flash 
         {
            reference_designators = "U5";
         }
         class = "altera_nios_dev_board_stratix_2s60";
         class_version = "5.0";
         device_family = "STRATIXII";
         device_is_engineering_sample = "1";
         quartus_pgm_file = "system/altera_nios_dev_board_stratix_2s60.sof";
         quartus_project_file = "system/altera_nios_dev_board_stratix_2s60.qpf";
         reference_designators = "U5";
         sopc_system_file = "system/altera_nios_dev_board_stratix_2s60.ptf";
      }
      hardcopy_compatible = "0";
      RESETS 
      {
         RESET reset
         {
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         RESET reset_n
         {
            BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
            {
               pin_assignment = "";
               component_pin = "use_quartus_pin_assignment";
            }
         }
      }
   }
   MODULE ext_ram_bus
   {
      class = "altera_avalon_tri_state_bridge";
      class_version = "5.11";
      SLAVE avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Register_Outgoing_Signals = "1";
            Register_Incoming_Signals = "1";
            MASTERED_BY cpu_1/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_1/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            Address_Group = "0";
            MASTERED_BY cpu_2/data_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_2/instruction_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Bridges_To = "avalon_slave";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Is_Bridge = "1";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "0";
         }
         Clock_Source = "sys_clk";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE ext_flash
   {
      class = "altera_avalon_cfi_flash";
      class_version = "5.11";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "8";
               is_shared = "1";
               direction = "inout";
               type = "data";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U5.35,U5.37,U5.39,U5.41,U5.44,U5.46,U5.48,U5.50";
                  pin_assignment = "E16,G15,E19,D20,G19,D19,E20,F20";
               }
               originally_shared = "1";
            }
            PORT address
            {
               width = "24";
               is_shared = "1";
               direction = "input";
               type = "address";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U5.51,U5.31,U5.26,U5.25,U5.24,U5.23,U5.22,U5.21,U5.20,U5.10,U5.9,U5.8,U5.7,U5.6,U5.5,U5.4,U5.3,U5.54,U5.19,U5.18,U5.11,U5.12,U5.15,U5.2";
                  pin_assignment = "T2,T3,U1,U2,V1,V2,W1,W2,Y1,Y2,AA1,AA2,AB1,AB2,W3,W4,Y3,Y4,AA3,AA4,AB3,AB4,AC2,AC3";
               }
               originally_shared = "1";
            }
            PORT read_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "read_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U5.34";
                  pin_assignment = "AB9";
               }
               originally_shared = "0";
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U5.13";
                  pin_assignment = "AD6";
               }
               originally_shared = "0";
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
               BOARD_COMPONENT altera_nios_dev_board_stratix_2s60
               {
                  component_pin = "U5.32";
                  pin_assignment = "AE4";
               }
               originally_shared = "0";
            }
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            flash_reference_designator = "U5";
            Supports_Flash_File_System = "1";
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Base_Address = "0x00000000";
            Data_Width = "8";
            Address_Width = "24";
            Write_Wait_States = "160ns";
            Read_Wait_States = "160ns";
            Setup_Time = "45ns";
            Hold_Time = "35ns";
            MASTERED_BY ext_ram_bus/tristate_master
            {
               priority = "1";
            }
            Is_Base_Locked = "1";
            Simulation_Num_Lanes = "1";
            Is_Nonvolatile_Storage = "1";
            Address_Span = "16777216";
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            Convert_Xs_To_0 = "1";
            Address_Group = "0";
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Make_Memory_Model = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sys_clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "45";
         Wait_Value = "160";
         Hold_Value = "35";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "16777216";
         MAKE 
         {
            TARGET flashfiles
            {
               ext_flash 
               {
                  Command1 = "@echo Post-processing to create $(notdir $@)";
                  Dependency = "$(ELF)";
                  Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
                  Command2 = "elf2flash --input=$(ELF) --flash=U5 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0xFFFFFF --reset=$(CPU_RESET_ADDRESS) ";
               }
            }
            MACRO 
            {
               EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
               EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
            }
            TARGET delete_placeholder_warning
            {
               ext_flash 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET sim
            {
               ext_flash 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
            MASTER cpu_1
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x0";
               }
            }
            MASTER cpu_2
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x40000";
               }
            }
         }
         contents_info = "SIMDIR/ext_flash.dat 1124882108 ";
      }
   }
   MODULE ext_ram
   {
      class = "altera_nios_dev_kit_stratix_edition_sram2";
      class_version = "5.1";
      iss_model_name = "altera_memory";
      HDL_INFO 
      {
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         sram_memory_size = "1024";
         sram_memory_units = "1024";
         sram_data_width = "32";
         MAKE 
         {
            TARGET delete_placeholder_warning
            {
               ext_ram 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET sim
            {
               ext_ram 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";