📄 std_1s40.ptf
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direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT dataavailable
{
Is_Enabled = "1";
direction = "output";
type = "dataavailable";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT read_n
{
Is_Enabled = "1";
direction = "input";
type = "read_n";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT readyfordata
{
Is_Enabled = "1";
direction = "output";
type = "readyfordata";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "sys_clk";
View
{
Settings_Summary = "8-bit UART with 115200 baud, <br> 1 stop bits and N parity";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = " Bus Interface";
format = "Divider";
}
SIGNAL b
{
name = "chipselect";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "writedata";
radix = "hexadecimal";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = " Internals";
format = "Divider";
}
SIGNAL g
{
name = "tx_ready";
}
SIGNAL h
{
name = "tx_data";
radix = "ascii";
}
SIGNAL i
{
name = "rx_char_ready";
}
SIGNAL j
{
name = "rx_data";
radix = "ascii";
}
}
INTERACTIVE_OUT log
{
enable = "0";
file = "_log_module.txt";
radix = "ascii";
signals = "temp,list";
exe = "perl -- tail-f.pl";
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "perl -- uart.pl";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
baud = "115200";
data_bits = "8";
fixed_baud = "1";
parity = "N";
stop_bits = "1";
use_cts_rts = "0";
use_eop_register = "0";
sim_true_baud = "0";
sim_char_stream = "";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart1.vhd";
Synthesis_Only_Files = "";
}
}
MODULE sysid
{
class = "altera_avalon_sysid";
class_version = "5.11";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "1";
Data_Width = "32";
Base_Address = "0x07110080";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Read_Latency = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu_3/data_master
{
priority = "1";
}
IRQ_MASTER cpu_3/data_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu_4/data_master
{
priority = "1";
}
IRQ_MASTER cpu_4/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
Top_Level_Ports_Are_Enumerated = "1";
View
{
Settings_Summary = "System ID (at last Generate):<br> <b>95294302</b> (unique ID tag) <br> <b>43EFDCA3</b> (timestamp: Mon Feb 13, 2006 @10:10 AM)";
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "sys_clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
id = "2502509314u";
timestamp = "1139793059u";
MAKE
{
TARGET verifysysid
{
verifysysid
{
All_Depends_On = "0";
Command = "nios2-download $(JTAG_CABLE) --sidp=0x07110080 --id=2502509314 --timestamp=1139793059";
Is_Phony = "1";
Target_File = "dummy_verifysysid_file";
}
}
}
}
}
MODULE pll
{
class = "altera_avalon_pll";
class_version = "5.11";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/pll.vhd, __PROJECT_DIRECTORY__/altpllpll.vhd";
Synthesis_Only_Files = "";
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Default_Module_Name = "pll";
Clock_Source = "clk";
Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
Settings_Summary = " Avalon PLL: <br> input clock configured: <b>clk</b> ";
}
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "0";
Read_Wait_States = "1";
Write_Wait_States = "0";
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Requires_Internal_Clock_Promotion = "Yes";
Is_Clock_Source = "1";
Base_Address = "0x071100A0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "0";
}
MASTERED_BY cpu_3/data_master
{
priority = "1";
}
IRQ_MASTER cpu_3/data_master
{
IRQ_Number = "0";
}
MASTERED_BY cpu_4/data_master
{
priority = "1";
}
IRQ_MASTER cpu_4/data_master
{
IRQ_Number = "0";
}
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT c0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT e0
{
Is_Enabled = "1";
direction = "output";
type = "out_clk";
width = "1";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT read
{
Is_Enabled = "1";
direction = "input";
type = "read";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT resetrequest
{
Is_Enabled = "1";
direction = "output";
type = "resetrequest";
width = "1";
}
PORT write
{
Is_Enabled = "1";
direction = "input";
type = "write";
width = "1";
}
PORT writedata
{
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