📄 std_1s40.ptf
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}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "4";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "4";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "1";
Address_Width = "2";
Data_Width = "4";
Base_Address = "0x07110000";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "5";
}
Address_Group = "0";
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "5";
}
MASTERED_BY cpu_3/data_master
{
priority = "1";
}
IRQ_MASTER cpu_3/data_master
{
IRQ_Number = "5";
}
MASTERED_BY cpu_4/data_master
{
priority = "1";
}
IRQ_MASTER cpu_4/data_master
{
IRQ_Number = "5";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "sys_clk";
View
{
Settings_Summary = " 4-bit PIO using <br> input pins with edge type ANY and interrupt source EDGE ";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "1";
Driven_Sim_Value = "0x000F";
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "1";
edge_type = "ANY";
irq_type = "EDGE";
}
}
MODULE led_pio
{
class = "altera_avalon_pio";
class_version = "5.11";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.vhd";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "8";
}
PORT out_port
{
direction = "output";
Is_Enabled = "1";
width = "8";
originally_shared = "0";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "D0-D7.D0,D0-D7.D1,D0-D7.D2,D0-D7.D3,D0-D7.D4,D0-D7.D5,D0-D7.D6,D0-D7.D7";
pin_assignment = "H27,H28,L23,L24,J25,J26,L20,L19";
}
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "8";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "8";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "8";
Base_Address = "0x07110010";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu_4/data_master
{
priority = "1";
}
IRQ_MASTER cpu_4/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "sys_clk";
View
{
Settings_Summary = " 8-bit PIO using <br> output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE seven_seg_pio
{
class = "altera_avalon_pio";
class_version = "5.11";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/seven_seg_pio.vhd";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "16";
}
PORT out_port
{
direction = "output";
Is_Enabled = "1";
width = "16";
originally_shared = "0";
is_shared = "0";
BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
{
component_pin = "U8-U9.G0,U8-U9.F0,U8-U9.E0,U8-U9.D0,U8-U9.C0,U8-U9.B0,U8-U9.A0,U8-U9.DP0,U8-U9.G1,U8-U9.F1,U8-U9.E1,U8-U9.D1,U8-U9.C1,U8-U9.B1,U8-U9.A1,U8-U9.DP1";
pin_assignment = "C21,B21,A21,C20,A20,B20,B18,D21,E19,C19,B19,A19,D18,C18,A18,D19";
}
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "16";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "16";
Base_Address = "0x07110020";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu_3/data_master
{
priority = "1";
}
IRQ_MASTER cpu_3/data_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu_4/data_master
{
priority = "1";
}
IRQ_MASTER cpu_4/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "sys_clk";
View
{
Settings_Summary = " 16-bit PIO using <br> output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE reconfig_request_pio
{
class = "altera_avalon_pio";
class_version = "5.11";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/reconfig_request_pio.vhd";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "1";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "1";
originally_shared = "0";
is_shared = "0";
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