std_1s40.ptf

FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

SYSTEM std_1s40
{
   System_Wizard_Version = "5.10";
   System_Wizard_Build = "213";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "STRATIX";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      board_class = "altera_nios_dev_board_stratix_1s40";
      CLOCKS 
      {
         CLOCK sys_clk
         {
            frequency = "50000000";
            source = "pll_c0";
            display_name = "sys_clk";
            Is_Clock_Source = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK pll_e0
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "e0 from pll";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK pll_c0
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from pll";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK sdram_clk_out
         {
            frequency = "50000000";
            source = "pll_e0";
            Is_Clock_Source = "0";
            display_name = "sdram_clk_out";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         CLOCK clk
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk";
            pipeline = "0";
            BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
      }
      hdl_language = "vhdl";
      device_family_id = "STRATIX";
      view_master_columns = "1";
      view_master_priorities = "0";
      name_column_width = "269";
      desc_column_width = "270";
      bustype_column_width = "0";
      base_column_width = "75";
      clock_column_width = "60";
      end_column_width = "75";
      BOARD_INFO 
      {
         CONFIGURATION factory
         {
            length = "";
            menu_position = "2";
            offset = "0x600000";
            reference_designator = "U5";
         }
         CONFIGURATION user
         {
            length = "";
            menu_position = "1";
            offset = "0x400000";
            reference_designator = "U5";
         }
         JTAG_device_index = "1";
         REFDES U5
         {
            base = "0x00800000";
         }
         altera_avalon_cfi_flash 
         {
            reference_designators = "U5";
         }
         class = "altera_nios_dev_board_stratix_1s40";
         class_version = "5.0";
         device_family = "STRATIX";
         quartus_pgm_file = "system/altera_nios_dev_board_stratix_1s40.sof";
         quartus_project_file = "system/altera_nios_dev_board_stratix_1s40.qpf";
         reference_designators = "U5";
         sopc_system_file = "system/altera_nios_dev_board_stratix_1s40.ptf";
      }
      RESETS 
      {
         RESET reset
         {
            BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
            {
               component_pin = "use_quartus_pin_assignment";
               pin_assignment = "";
            }
         }
         RESET reset_n
         {
            BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
            {
               pin_assignment = "";
               component_pin = "use_quartus_pin_assignment";
            }
         }
      }
      view_frame_window = "160:150:1280:900";
      do_log_history = "0";
   }
   MODULE ext_ram_bus
   {
      class = "altera_avalon_tri_state_bridge";
      class_version = "5.11";
      SLAVE avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Register_Outgoing_Signals = "1";
            Register_Incoming_Signals = "1";
            MASTERED_BY cpu_1/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_1/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            Address_Group = "0";
            MASTERED_BY cpu_2/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_2/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
            MASTERED_BY cpu_3/data_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_3/instruction_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_3/data_master
            {
               IRQ_Number = "NC";
            }
            MASTERED_BY cpu_4/data_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_4/instruction_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_4/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Bridges_To = "avalon_slave";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sys_clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "0";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE ext_flash
   {
      class = "altera_avalon_cfi_flash";
      class_version = "5.11";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "8";
               is_shared = "1";
               direction = "inout";
               type = "data";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
               {
                  component_pin = "U5.31,U5.32,U5.33,U5.34,U5.38,U5.39,U5.40,U5.41";
                  pin_assignment = "H12,F12,J12,M12,H17,K18,H18,G18";
               }
            }
            PORT address
            {
               width = "23";
               is_shared = "1";
               direction = "input";
               type = "address";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
               {
                  component_pin = "U5.27,U5.22,U5.21,U5.20,U5.19,U5.18,U5.17,U5.16,U5.10,U5.9,U5.42,U5.8,U5.7,U5.6,U5.5,U5.4,U5.3,U5.46,U5.15,U5.43,U5.44,U5.35,U5.2";
                  pin_assignment = "A4,A3,B3,B5,B4,C4,A5,C5,D5,E6,A6,B7,D6,A7,D7,C6,C7,B6,D8,C8,E8,D9,B9";
               }
            }
            PORT read_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "read_n";
               originally_shared = "1";
               BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
               {
                  component_pin = "U5.30";
                  pin_assignment = "F19";
               }
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
               {
                  component_pin = "U5.11";
                  pin_assignment = "G19";
               }
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
               originally_shared = "0";
               BOARD_COMPONENT altera_nios_dev_board_stratix_1s40
               {
                  component_pin = "U5.28";
                  pin_assignment = "K19";
               }
            }
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            Supports_Flash_File_System = "1";
            flash_reference_designator = "U5";
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Nonvolatile_Storage = "1";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Base_Address = "0x00000000";
            Data_Width = "8";
            Address_Width = "23";
            Simulation_Num_Lanes = "1";
            Convert_Xs_To_0 = "1";
            Write_Wait_States = "160ns";
            Read_Wait_States = "160ns";
            Setup_Time = "40ns";
            Hold_Time = "40ns";
            Address_Span = "8388608";
            MASTERED_BY ext_ram_bus/tristate_master
            {
               priority = "1";
            }
            Is_Base_Locked = "1";
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            Address_Group = "0";
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
            IRQ_MASTER cpu_3/data_master
            {
               IRQ_Number = "NC";
            }
            IRQ_MASTER cpu_4/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Make_Memory_Model = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "sys_clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "40";
         Wait_Value = "160";
         Hold_Value = "40";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "8388608";
         MAKE 
         {
            MACRO 
            {
               EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
               EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
            }
            TARGET delete_placeholder_warning
            {
               ext_flash 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET flashfiles
            {
               ext_flash 
               {
                  Command1 = "@echo Post-processing to create $(notdir $@)";
                  Command2 = "elf2flash --input=$(ELF) --flash=U5 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
                  Dependency = "$(ELF)";
                  Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
               }
            }
            TARGET sim
            {
               ext_flash 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
            MASTER cpu_1
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x0";
               }
            }
            MASTER cpu_2
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x40000";
               }
            }
            MASTER cpu_3
            {
               MACRO 
               {
                  BOOT_COPIER = "boot_loader_cfi.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x80000";
               }
            }
            MASTER cpu_4