📄 std_1c20.ptf
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}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "1";
Base_Address = "0x00C00040";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Settings_Summary = " 1-bit PIO using <br>
tri-state pins with edge type NONE and interrupt source NONE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
has_tri = "1";
has_out = "0";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
}
}
MODULE sysid
{
class = "altera_avalon_sysid";
class_version = "4.0";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "1";
Data_Width = "32";
Base_Address = "0x00C00050";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Read_Latency = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
View
{
Settings_Summary = "System ID (at last Generate):<br> <b>604507E8</b> (unique ID tag) <br> <b>42C6722A</b> (timestamp: Sat Jul 2, 2005 @7:53 PM)";
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
value0 = "3165772932u";
value1 = "1077149968u";
MAKE
{
TARGET verifysysid
{
verifysysid
{
All_Depends_On = "0";
Command = "nios2-download $(JTAG_CABLE) --sidp=0x00C00050 --id=1615136744 --timestamp=1120301610";
Target_File = "dummy_verifysysid_file";
Is_Phony = "1";
}
}
}
id = "1615136744u";
timestamp = "1120301610u";
}
}
MODULE uart1
{
class = "altera_avalon_uart";
class_version = "4.2";
iss_model_name = "altera_avalon_uart";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
Base_Address = "0x00C00060";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "4";
}
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "4";
}
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
Is_Enabled = "1";
}
PORT begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT read_n
{
direction = "input";
type = "read_n";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
Is_Enabled = "1";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
Is_Enabled = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
View
{
Settings_Summary = "8-bit UART with 115200 baud, <br>
1 stop bits and N parity";
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = " Bus Interface";
format = "Divider";
}
SIGNAL b
{
name = "chipselect";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "writedata";
radix = "hexadecimal";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = " Internals";
format = "Divider";
}
SIGNAL g
{
name = "tx_ready";
}
SIGNAL h
{
name = "tx_data";
radix = "ascii";
}
SIGNAL i
{
name = "rx_char_ready";
}
SIGNAL j
{
name = "rx_data";
radix = "ascii";
}
}
INTERACTIVE_OUT log
{
enable = "0";
file = "_log_module.txt";
radix = "ascii";
signals = "temp,list";
exe = "perl -- tail-f.pl";
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "perl -- uart.pl";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
baud = "115200";
data_bits = "8";
fixed_baud = "1";
parity = "N";
stop_bits = "1";
use_cts_rts = "0";
use_eop_register = "0";
sim_true_baud = "0";
sim_char_stream = "";
}
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart1.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT rxd
{
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT txd
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT cts_n
{
direction = "input";
width = "1";
Is_Enabled = "0";
}
PORT rts_n
{
direction = "output";
width = "1";
Is_Enabled = "0";
}
}
}
MODULE sdram
{
class = "altera_avalon_new_sdram_controller";
class_version = "4.2";
iss_model_name = "altera_memory";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Maximum_Pending_Read_Transactions = "7";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "pe⌨️ 快捷键说明
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