std_1c20.ptf

FDMP the body of the kernel, the Information-Technology Promotion Agency (IPA) adopted by the unexpl

            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "16";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "2";
            Data_Width = "16";
            Base_Address = "0x00C00010";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu_1/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            MASTERED_BY cpu_2/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         View 
         {
            Settings_Summary = " 16-bit PIO using <br>
					
					
					 output pins";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Wire_Test_Bench_Values = "1";
         Clock_Source = "clk";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0x0000";
      }
   }
   MODULE led_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";
      HDL_INFO 
      {
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_pio.vhd";
         Precompiled_Simulation_Library_Files = "";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT out_port
         {
            direction = "output";
            width = "8";
            Is_Enabled = "1";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "4";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "4";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "2";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "8";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "2";
            Data_Width = "8";
            Base_Address = "0x00C00020";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            MASTERED_BY cpu_1/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            MASTERED_BY cpu_2/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         View 
         {
            Settings_Summary = " 8-bit PIO using <br>
					
					
					 output pins";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Wire_Test_Bench_Values = "1";
         Clock_Source = "clk";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0x0000";
      }
   }
   MODULE lcd_display
   {
      class = "altera_avalon_lcd_16207";
      class_version = "4.0";
      HDL_INFO 
      {
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd_display.vhd";
         Precompiled_Simulation_Library_Files = "";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT LCD_E
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
         }
         PORT LCD_RS
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
         }
         PORT LCD_RW
         {
            direction = "output";
            width = "1";
            Is_Enabled = "1";
         }
         PORT LCD_data
         {
            direction = "inout";
            width = "8";
            Is_Enabled = "1";
         }
      }
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "2";
               Is_Enabled = "1";
            }
            PORT begintransfer
            {
               direction = "input";
               type = "begintransfer";
               width = "1";
               Is_Enabled = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
               Is_Enabled = "1";
            }
            PORT read
            {
               direction = "input";
               type = "read";
               width = "1";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "8";
               Is_Enabled = "1";
            }
            PORT write
            {
               direction = "input";
               type = "write";
               width = "1";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               direction = "input";
               type = "writedata";
               width = "8";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Is_Printable_Device = "1";
            Address_Width = "2";
            Data_Width = "8";
            Base_Address = "0x00C00030";
            Address_Alignment = "native";
            Read_Wait_States = "250ns";
            Write_Wait_States = "250ns";
            Setup_Time = "250ns";
            Hold_Time = "250ns";
            Read_Latency = "0";
            MASTERED_BY cpu_1/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_1/data_master
            {
               IRQ_Number = "NC";
            }
            MASTERED_BY cpu_2/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_2/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         View 
         {
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Clock_Source = "clk";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE reconfig_request_pio
   {
      class = "altera_avalon_pio";
      class_version = "2.2";
      HDL_INFO 
      {
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/reconfig_request_pio.vhd";
         Precompiled_Simulation_Library_Files = "";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            direction = "inout";
            width = "1";
            Is_Enabled = "1";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "4";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "4";
         }
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "2";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               direction = "input";
               type = "chipselect";
               width = "1";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";