📄 std_1c20.ptf
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numslaves = "1";
ismaster = "1";
clockpolarity = "0";
clockphase = "0";
lsbfirst = "0";
extradelay = "1";
targetssdelay = "100";
delayunits = "us";
delaymult = "1e-006";
prefix = "epcs_";
MAKE
{
MACRO
{
EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";
EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
EPCS_RELOCATE = "$(EPCS_RELOCATE_TMP:1=--relocate)";
EPCS_RELOCATE_TMP = "$(BOOTS_FROM_EPCS:0=)";
}
TARGET epcs
{
epcs_controller
{
All_Depends_On = "0";
Command1 = "sof2flash --flash=U59 --offset=0x0 --output=epcs.flash $(SOF) --epcs ";
Command2 = "nios2-flash-programmer --input=epcs.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs $(EPCS_RELOCATE) ";
Dependency = "";
Is_Phony = "1";
Target_File = "epcs_controller_boot_rom_epcs_configuration";
}
}
TARGET flashfiles
{
epcs_controller
{
Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash=U59 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER_EPCS) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF ; fi";
Dependency = "$(ELF)";
Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
}
}
TARGET programflash
{
epcs_controller
{
All_Depends_On = "0";
Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs ; fi";
Dependency = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
Is_Phony = "1";
Target_File = "epcs_controller_boot_rom_programflash";
}
}
TARGET delete_placeholder_warning
{
epcs_controller
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET programflashnoelfdependency
{
epcs_controller
{
All_Depends_On = "0";
Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs ; fi";
Is_Phony = "1";
Target_File = "epcs_controller_boot_rom_programflashnoelf";
}
}
TARGET sim
{
epcs_controller
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
MASTER cpu_1
{
MACRO
{
BOOTS_FROM_EPCS = "0";
BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
MASTER cpu_2
{
MACRO
{
BOOTS_FROM_EPCS = "0";
BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x40000";
}
}
}
clockunit = "kHz";
delayunit = "us";
register_offset = "0x200";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.vhd";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE lan91c111
{
class = "altera_avalon_lan91c111";
class_version = "2.3";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT LAN91C111_REGISTERS_OFFSET
{
value = "0x0300";
comment = "offset 0 or 0x300, depending on address bus wiring";
}
CONSTANT LAN91C111_DATA_BUS_WIDTH
{
value = "32";
comment = "width 16 or 32, depending on data bus wiring";
}
}
Is_Ethernet_Mac = "1";
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Wire_Test_Bench_Values = "1";
Is_Enabled = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "0";
Is_Enabled = "1";
Is_Bus_Master = "0";
Bus_Type = "avalon_tristate";
Uses_Tri_State_Data_Bus = "1";
Address_Alignment = "native";
Address_Width = "14";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "20ns";
Write_Wait_States = "20ns";
Setup_Time = "20ns";
Hold_Time = "20ns";
Is_Memory_Device = "0";
Date_Modified = "2002.03.19.10:51:51";
Base_Address = "0x00B00000";
Tri_State_Data_Bus = "--unknown--";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "6";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT irq
{
direction = "output";
width = "1";
type = "irq";
test_bench_value = "0";
}
PORT byteenablen
{
is_shared = "1";
direction = "input";
width = "4";
type = "byteenable_n";
}
PORT address
{
is_shared = "1";
direction = "input";
width = "14";
type = "address";
lsb = "2";
}
PORT data
{
is_shared = "1";
direction = "inout";
width = "32";
type = "data";
}
PORT iow_n
{
direction = "input";
width = "1";
type = "write_n";
}
PORT ior_n
{
direction = "input";
width = "1";
type = "read_n";
}
PORT reset_n
{
direction = "input";
width = "1";
type = "reset_n";
Is_Enabled = "0";
}
PORT reset
{
direction = "input";
width = "1";
type = "reset";
}
PORT ardy
{
direction = "output";
width = "1";
type = "inhibitrequest_n";
Is_Enabled = "0";
}
}
}
}
MODULE button_pio
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
width = "4";
test_bench_value = "15";
Is_Enabled = "1";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "4";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "4";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "4";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "4";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "1";
Address_Width = "2";
Data_Width = "4";
Base_Address = "0x00C00000";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_1/data_master
{
priority = "1";
}
IRQ_MASTER cpu_1/data_master
{
IRQ_Number = "2";
}
MASTERED_BY cpu_2/data_master
{
priority = "1";
}
IRQ_MASTER cpu_2/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Settings_Summary = " 4-bit PIO using <br>
input pins with edge type ANY and interrupt source EDGE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
Wire_Test_Bench_Values = "1";
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "1";
edge_type = "ANY";
irq_type = "EDGE";
Do_Test_Bench_Wiring = "1";
Driven_Sim_Value = "0x000F";
}
}
MODULE seven_seg_pio
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/seven_seg_pio.vhd";
Precompiled_Simulation_Library_Files = "";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT out_port
{
direction = "output";
width = "16";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "4";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "4";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
Is_Enabled = "1";
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