📄 ioat90usb1287.h
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/* TCNT0 - Timer/Counter0 */
#define TCNT0_0 0 //
#define TCNT0_1 1 //
#define TCNT0_2 2 //
#define TCNT0_3 3 //
#define TCNT0_4 4 //
#define TCNT0_5 5 //
#define TCNT0_6 6 //
#define TCNT0_7 7 //
/* OCR0A - Timer/Counter0 Output Compare Register */
#define OCROA_0 0 //
#define OCROA_1 1 //
#define OCROA_2 2 //
#define OCROA_3 3 //
#define OCROA_4 4 //
#define OCROA_5 5 //
#define OCROA_6 6 //
#define OCROA_7 7 //
/* OCR0B - Timer/Counter0 Output Compare Register */
#define OCR0B_0 0 //
#define OCR0B_1 1 //
#define OCR0B_2 2 //
#define OCR0B_3 3 //
#define OCR0B_4 4 //
#define OCR0B_5 5 //
#define OCR0B_6 6 //
#define OCR0B_7 7 //
/* GTCCR - General Timer/Counter Control Register */
#define PSRSYNC 0 // Prescaler Reset Timer/Counter1 and Timer/Counter0
#define PSR10 PSRSYNC // For compatibility
#define TSM 7 // Timer/Counter Synchronization Mode
/* ***** TIMER_COUNTER_2 ************** */
/* TIMSK2 - Timer/Counter Interrupt Mask register */
#define TOIE2 0 // Timer/Counter2 Overflow Interrupt Enable
#define TOIE2A TOIE2 // For compatibility
#define OCIE2A 1 // Timer/Counter2 Output Compare Match A Interrupt Enable
#define OCIE2B 2 // Timer/Counter2 Output Compare Match B Interrupt Enable
/* TIFR2 - Timer/Counter Interrupt Flag Register */
#define TOV2 0 // Timer/Counter2 Overflow Flag
#define OCF2A 1 // Output Compare Flag 2A
#define OCF2B 2 // Output Compare Flag 2B
/* TCCR2A - Timer/Counter2 Control Register A */
#define WGM20 0 // Waveform Genration Mode
#define WGM21 1 // Waveform Genration Mode
#define COM2B0 4 // Compare Output Mode bit 0
#define COM2B1 5 // Compare Output Mode bit 1
#define COM2A0 6 // Compare Output Mode bit 1
#define COM2A1 7 // Compare Output Mode bit 1
/* TCCR2B - Timer/Counter2 Control Register B */
#define CS20 0 // Clock Select bit 0
#define CS21 1 // Clock Select bit 1
#define CS22 2 // Clock Select bit 2
#define WGM22 3 // Waveform Generation Mode
#define FOC2B 6 // Force Output Compare B
#define FOC2A 7 // Force Output Compare A
/* TCNT2 - Timer/Counter2 */
#define TCNT2_0 0 // Timer/Counter 2 bit 0
#define TCNT2_1 1 // Timer/Counter 2 bit 1
#define TCNT2_2 2 // Timer/Counter 2 bit 2
#define TCNT2_3 3 // Timer/Counter 2 bit 3
#define TCNT2_4 4 // Timer/Counter 2 bit 4
#define TCNT2_5 5 // Timer/Counter 2 bit 5
#define TCNT2_6 6 // Timer/Counter 2 bit 6
#define TCNT2_7 7 // Timer/Counter 2 bit 7
/* OCR2A - Timer/Counter2 Output Compare Register A */
#define OCR2_0 0 // Timer/Counter2 Output Compare Register Bit 0
#define OCR2_1 1 // Timer/Counter2 Output Compare Register Bit 1
#define OCR2_2 2 // Timer/Counter2 Output Compare Register Bit 2
#define OCR2_3 3 // Timer/Counter2 Output Compare Register Bit 3
#define OCR2_4 4 // Timer/Counter2 Output Compare Register Bit 4
#define OCR2_5 5 // Timer/Counter2 Output Compare Register Bit 5
#define OCR2_6 6 // Timer/Counter2 Output Compare Register Bit 6
#define OCR2_7 7 // Timer/Counter2 Output Compare Register Bit 7
/* OCR2B - Timer/Counter2 Output Compare Register B */
//#define OCR2_0 0 // Timer/Counter2 Output Compare Register Bit 0
//#define OCR2_1 1 // Timer/Counter2 Output Compare Register Bit 1
//#define OCR2_2 2 // Timer/Counter2 Output Compare Register Bit 2
//#define OCR2_3 3 // Timer/Counter2 Output Compare Register Bit 3
//#define OCR2_4 4 // Timer/Counter2 Output Compare Register Bit 4
//#define OCR2_5 5 // Timer/Counter2 Output Compare Register Bit 5
//#define OCR2_6 6 // Timer/Counter2 Output Compare Register Bit 6
//#define OCR2_7 7 // Timer/Counter2 Output Compare Register Bit 7
/* ASSR - Asynchronous Status Register */
#define TCR2BUB 0 // Timer/Counter Control Register2 Update Busy
#define TCR2AUB 1 // Timer/Counter Control Register2 Update Busy
#define OCR2BUB 2 // Output Compare Register 2 Update Busy
#define OCR2AUB 3 // Output Compare Register2 Update Busy
#define TCN2UB 4 // Timer/Counter2 Update Busy
#define AS2 5 // Asynchronous Timer/Counter2
#define EXCLK 6 // Enable External Clock Input
/* GTCCR - General Timer Counter Control register */
#define PSRASY 1 // Prescaler Reset Timer/Counter2
#define PSR2 PSRASY // For compatibility
//#define TSM 7 // Timer/Counter Synchronization Mode
/* ***** TIMER_COUNTER_3 ************** */
/* TIMSK3 - Timer/Counter3 Interrupt Mask Register */
#define TOIE3 0 // Timer/Counter3 Overflow Interrupt Enable
#define OCIE3A 1 // Timer/Counter3 Output Compare A Match Interrupt Enable
#define OCIE3B 2 // Timer/Counter3 Output Compare B Match Interrupt Enable
#define OCIE3C 3 // Timer/Counter3 Output Compare C Match Interrupt Enable
#define ICIE3 5 // Timer/Counter3 Input Capture Interrupt Enable
/* TIFR3 - Timer/Counter3 Interrupt Flag register */
#define TOV3 0 // Timer/Counter3 Overflow Flag
#define OCF3A 1 // Output Compare Flag 3A
#define OCF3B 2 // Output Compare Flag 3B
#define OCF3C 3 // Output Compare Flag 3C
#define ICF3 5 // Input Capture Flag 3
/* TCCR3A - Timer/Counter3 Control Register A */
#define WGM30 0 // Waveform Generation Mode
#define WGM31 1 // Waveform Generation Mode
#define COM3C0 2 // Compare Output Mode 3C, bit 0
#define COM3C1 3 // Compare Output Mode 3C, bit 1
#define COM3B0 4 // Compare Output Mode 3B, bit 0
#define COM3B1 5 // Compare Output Mode 3B, bit 1
#define COM3A0 6 // Compare Output Mode 3A, bit 0
#define COM3A1 7 // Compare Output Mode 1A, bit 1
/* TCCR3B - Timer/Counter3 Control Register B */
#define CS30 0 // Prescaler source of Timer/Counter 3
#define CS31 1 // Prescaler source of Timer/Counter 3
#define CS32 2 // Prescaler source of Timer/Counter 3
#define WGM32 3 // Waveform Generation Mode
#define WGM33 4 // Waveform Generation Mode
#define ICES3 6 // Input Capture 3 Edge Select
#define ICNC3 7 // Input Capture 3 Noise Canceler
/* TCCR3C - Timer/Counter 3 Control Register C */
#define FOC3C 5 // Force Output Compare 3C
#define FOC3B 6 // Force Output Compare 3B
#define FOC3A 7 // Force Output Compare 3A
/* ***** TIMER_COUNTER_1 ************** */
/* TIMSK1 - Timer/Counter1 Interrupt Mask Register */
#define TOIE1 0 // Timer/Counter1 Overflow Interrupt Enable
#define OCIE1A 1 // Timer/Counter1 Output Compare A Match Interrupt Enable
#define OCIE1B 2 // Timer/Counter1 Output Compare B Match Interrupt Enable
#define OCIE1C 3 // Timer/Counter1 Output Compare C Match Interrupt Enable
#define ICIE1 5 // Timer/Counter1 Input Capture Interrupt Enable
/* TIFR1 - Timer/Counter1 Interrupt Flag register */
#define TOV1 0 // Timer/Counter1 Overflow Flag
#define OCF1A 1 // Output Compare Flag 1A
#define OCF1B 2 // Output Compare Flag 1B
#define OCF1C 3 // Output Compare Flag 1C
#define ICF1 5 // Input Capture Flag 1
/* TCCR1A - Timer/Counter1 Control Register A */
#define WGM10 0 // Waveform Generation Mode
#define WGM11 1 // Waveform Generation Mode
#define COM1C0 2 // Compare Output Mode 1C, bit 0
#define COM1C1 3 // Compare Output Mode 1C, bit 1
#define COM1B0 4 // Compare Output Mode 1B, bit 0
#define COM1B1 5 // Compare Output Mode 1B, bit 1
#define COM1A0 6 // Compare Output Mode 1A, bit 0
#define COM1A1 7 // Compare Output Mode 1A, bit 1
/* TCCR1B - Timer/Counter1 Control Register B */
#define CS10 0 // Prescaler source of Timer/Counter 1
#define CS11 1 // Prescaler source of Timer/Counter 1
#define CS12 2 // Prescaler source of Timer/Counter 1
#define WGM12 3 // Waveform Generation Mode
#define WGM13 4 // Waveform Generation Mode
#define ICES1 6 // Input Capture 1 Edge Select
#define ICNC1 7 // Input Capture 1 Noise Canceler
/* TCCR1C - Timer/Counter 1 Control Register C */
#define FOC1C 5 // Force Output Compare 1C
#define FOC1B 6 // Force Output Compare 1B
#define FOC1A 7 // Force Output Compare 1A
/* ***** JTAG ************************* */
/* OCDR - On-Chip Debug Related Register in I/O Memory */
#define OCDR0 0 // On-Chip Debug Register Bit 0
#define OCDR1 1 // On-Chip Debug Register Bit 1
#define OCDR2 2 // On-Chip Debug Register Bit 2
#define OCDR3 3 // On-Chip Debug Register Bit 3
#define OCDR4 4 // On-Chip Debug Register Bit 4
#define OCDR5 5 // On-Chip Debug Register Bit 5
#define OCDR6 6 // On-Chip Debug Register Bit 6
#define OCDR7 7 // On-Chip Debug Register Bit 7
#define IDRD OCDR7 // For compatibility
/* MCUCR - MCU Control Register */
//#define JTD 7 // JTAG Interface Disable
/* MCUSR - MCU Status Register */
//#define JTRF 4 // JTAG Reset Flag
/* ***** EXTERNAL_INTERRUPT *********** */
/* EICRA - External Interrupt Control Register A */
#define ISC00 0 // External Interrupt Sense Control Bit
#define ISC01 1 // External Interrupt Sense Control Bit
#define ISC10 2 // External Interrupt Sense Control Bit
#define ISC11 3 // External Interrupt Sense Control Bit
#define ISC20 4 // External Interrupt Sense Control Bit
#define ISC21 5 // External Interrupt Sense Control Bit
#define ISC30 6 // External Interrupt Sense Control Bit
#define ISC31 7 // External Interrupt Sense Control Bit
/* EICRB - External Interrupt Control Register B */
#define ISC40 0 // External Interrupt 7-4 Sense Control Bit
#define ISC41 1 // External Interrupt 7-4 Sense Control Bit
#define ISC50 2 // External Interrupt 7-4 Sense Control Bit
#define ISC51 3 // External Interrupt 7-4 Sense Control Bit
#define ISC60 4 // External Interrupt 7-4 Sense Control Bit
#define ISC61 5 // External Interrupt 7-4 Sense Control Bit
#define ISC70 6 // External Interrupt 7-4 Sense Control Bit
#define ISC71 7 // External Interrupt 7-4 Sense Control Bit
/* EIMSK - External Interrupt Mask Register */
#define INT0 0 // External Interrupt Request 0 Enable
#define INT1 1 // External Interrupt Request 1 Enable
#define INT2 2 // External Interrupt Request 2 Enable
#define INT3 3 // External Interrupt Request 3 Enable
#define INT4 4 // External Interrupt Request 4 Enable
#define INT5 5 // External Interrupt Request 5 Enable
#define INT6 6 // External Interrupt Request 6 Enable
#define INT7 7 // External Interrupt Request 7 Enable
/* EIFR - External Interrupt Flag Register */
#define INTF0 0 // External Interrupt Flag 0
#define INTF1 1 // External Interrupt Flag 1
#define INTF2 2 // External Interrupt Flag 2
#define INTF3 3 // External Interrupt Flag 3
#define INTF4 4 // External Interrupt Flag 4
#define INTF5 5 // External Interrupt Flag 5
#define INTF6 6 // External Interrupt Flag 6
#define INTF7 7 // External Interrupt Flag 7
/* PCICR - Pin Change Interrupt Control Register */
#define PCIE0 0 // Pin Change Interrupt Enable 0
#define PCIE1 1 // Pin Change Interrupt Enable 1
#define PCIE2 2 // Pin Change Interrupt Enable 2
/* PCIFR - Pin Change Interrupt Flag Register */
#define PCIF0 0 // Pin Change Interrupt Flag 0
#define PCIF1 1 // Pin Change Interrupt Flag 1
#define PCIF2 2 // Pin Change Interrupt Flag 2
/* PCMSK0 - Pin Change Mask Register 0 */
#define PCINT0 0 // Pin Change Enable Mask 0
#define PCINT1 1 // Pin Change Enable Mask 1
#define PCINT2 2 // Pin Change Enable Mask 2
#define PCINT3 3 // Pin Change Enable Mask 3
#define PCINT4 4 // Pin Change Enable Mask 4
#define PCINT5 5 // Pin Change Enable Mask 5
#define PCINT6 6 // Pin Change Enable Mask 6
#define PCINT7 7 // Pin Change Enable Mask 7
/* ***** AD_CONVERTER ***************** */
/* ADMUX - The ADC multiplexer Selection Register */
#define MUX0 0 // Analog Channel and Gain Selection Bits
#define MUX1 1 // Analog Channel and Gain Selection Bits
#define MUX2 2 // Analog Channel and Gain Selection Bits
#define MUX3 3 // Analog Channel and Gain Selection Bits
#define MUX4 4 // Analog Channel and Gain Selection Bits
#define ADLAR 5 // Left Adjust Result
#define REFS0 6 // Reference Selection Bit 0
#define REFS1 7 // Reference Selection Bit 1
/* ADCSRA - The ADC Control and Status register */
#define ADPS0 0 // ADC Prescaler Select Bits
#define ADPS1 1 // ADC Prescaler Select Bits
#define ADPS2 2 // ADC Prescaler Select Bits
#define ADIE 3 // ADC Interrupt Enable
#define ADIF 4 // ADC Interrupt Flag
#define ADATE 5 // ADC Auto Trigger Enable
#define ⌨️ 快捷键说明
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