📄 ioat90usb1287.h
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#define OTGTCON_7 7 //
/* OTGCON - */
#define VBUSRQC 0 //
#define VBUSREQ 1 //
#define VBUSHWC 2 //
#define SRPSEL 3 //
#define SRPREQ 4 //
#define HNPREQ 5 //
/* OTGIEN - */
#define SRPE 0 //
#define VBERRE 1 //
#define BCERRE 2 //
#define ROLEEXE 3 //
#define HNPERRE 4 //
#define STOE 5 //
/* OTGINT - */
#define SRPI 0 //
#define VBERRI 1 //
#define BCERRI 2 //
#define ROLEEXI 3 //
#define HNPERRI 4 //
#define STOI 5 //
/* ***** USB_HOST ********************* */
/* UHCON - */
#define SOFEN 0 //
#define RESET 1 //
#define RESUME 2 //
/* UHINT - */
#define DCONNI 0 //
#define DDISCI 1 //
#define RSTI 2 //
#define RSMEDI 3 //
#define RXRSMI 4 //
#define HSOFI 5 //
#define HWUPI 6 //
/* UHIEN - */
#define HWUPE 6
#define HSOFE 5
#define RXRSME 4
#define RSMEDE 3
#define RSTE 2
#define DDISCE 1
#define DCONNE 0
/* UHADDR - */
#define UHADDR_0 0 //
#define UHADDR_1 1 //
#define UHADDR_2 2 //
#define UHADDR_3 3 //
#define UHADDR_4 4 //
#define UHADDR_5 5 //
#define UHADDR_6 6 //
/* UHFNUMH - */
#define UHFNUMH_0 0 //
#define UHFNUMH_1 1 //
#define UHFNUMH_2 2 //
/* UHFNUML - */
#define UHFNUML_0 0 //
#define UHFNUML_1 1 //
#define UHFNUML_2 2 //
#define UHFNUML_3 3 //
#define UHFNUML_4 4 //
#define UHFNUML_5 5 //
#define UHFNUML_6 6 //
#define UHFNUML_7 7 //
/* UHFLEN - */
#define UHFLEN_0 0 //
#define UHFLEN_1 1 //
#define UHFLEN_2 2 //
#define UHFLEN_3 3 //
#define UHFLEN_4 4 //
#define UHFLEN_5 5 //
#define UHFLEN_6 6 //
#define UHFLEN_7 7 //
/* UPINRQX - */
#define INRQ0 0 //
#define INRQ1 1 //
#define INRQ2 2 //
#define INRQ3 3 //
#define INRQ4 4 //
#define INRQ5 5 //
#define INRQ6 6 //
#define INRQ7 7 //
/* UPINTX - */
#define RXINI 0 //
#define RXSTALLI 1 //
#define TXOUTI 2 //
#define TXSTPI 3 //
#define PERRI 4 //
//#define RWAL 5 //
#define NAKEDI 6 //
//#define FIFOCON 7 //
/* UPNUM - */
#define PNUM0 0 //
#define PNUM1 1 //
#define PNUM2 2 //
/* UPRST - */
#define PRST0 0 //
#define PRST1 1 //
#define PRST2 2 //
#define PRST3 3 //
#define PRST4 4 //
#define PRST5 5 //
#define PRST6 6 //
/* UPCONX - */
#define PEN 0 //
//#define RSTDT 3 //
#define INMODE 5 //
#define PFREEZE 6 //
/* UPCFG0X - */
#define PEPNUM0 0 //
#define PEPNUM1 1 //
#define PEPNUM2 2 //
#define PEPNUM3 3 //
#define PTOKEN0 4 //
#define PTOKEN1 5 //
#define PTYPE0 6 //
#define PTYPE1 7 //
/* UPCFG1X - */
//#define ALLOC 1 //
#define PBK0 2 //
#define PBK1 3 //
#define PSIZE0 4 //
#define PSIZE1 5 //
#define PSIZE2 6 //
/* UPSTAX - */
#define NBUSYK0 0 //
#define NBUSYK1 1 //
//#define DTSEQ0 2 //
//#define DTSEQ1 3 //
//#define UNDERFI 5 //
//#define OVERFI 6 //
//#define CFGOK 7 //
/* UPCFG2X - */
#define UPCFG2X_0 0 //
#define UPCFG2X_1 1 //
#define UPCFG2X_2 2 //
#define UPCFG2X_3 3 //
#define UPCFG2X_4 4 //
#define UPCFG2X_5 5 //
#define UPCFG2X_6 6 //
#define UPCFG2X_7 7 //
/* UPIENX - */
#define RXINE 0 //
#define RXSTALLE 1 //
#define TXOUTE 2 //
#define TXSTPE 3 //
#define PERRE 4 //
#define NAKEDE 6 //
//#define FLERRE 7 //
/* UPDATX - */
#define PDAT0 0 //
#define PDAT1 1 //
#define PDAT2 2 //
#define PDAT3 3 //
#define PDAT4 4 //
#define PDAT5 5 //
#define PDAT6 6 //
#define PDAT7 7 //
/* UPBCLX - */
#define PBYCT0 0 //
#define PBYCT1 1 //
#define PBYCT2 2 //
#define PBYCT3 3 //
#define PBYCT4 4 //
#define PBYCT5 5 //
#define PBYCT6 6 //
#define PBYCT7 7 //
/* UPBCHX - */
#define PBYCT8 0 //
#define PBYCT9 1 //
#define PBYCT10 2 //
/* UPINT - */
#define PINT0 0 //
#define PINT1 1 //
#define PINT2 2 //
#define PINT3 3 //
#define PINT4 4 //
#define PINT5 5 //
#define PINT6 6 //
/* UPERRX - */
#define DATATGL 0 //
#define DATAPID 1 //
#define PID 2 //
#define TIMEOUT 3 //
#define CRC16 4 //
#define COUNTER0 5 //
#define COUNTER1 6 //
/* ***** BOOT_LOAD ******************** */
/* SPMCSR - Store Program Memory Control Register */
#define SPMEN 0 // Store Program Memory Enable
#define PGERS 1 // Page Erase
#define PGWRT 2 // Page Write
#define BLBSET 3 // Boot Lock Bit Set
#define RWWSRE 4 // Read While Write section read enable
#define SIGRD 5 // Signature Row Read
#define RWWSB 6 // Read While Write Section Busy
#define SPMIE 7 // SPM Interrupt Enable
/* ***** EEPROM *********************** */
/* EEARH - EEPROM Address Register Low Byte */
#define EEAR8 0 // EEPROM Read/Write Access Bit 8
#define EEAR9 1 // EEPROM Read/Write Access Bit 9
#define EEAR10 2 // EEPROM Read/Write Access Bit 10
#define EEAR11 3 // EEPROM Read/Write Access Bit 11
/* EEARL - EEPROM Address Register Low Byte */
#define EEAR0 0 // EEPROM Read/Write Access Bit 0
#define EEAR1 1 // EEPROM Read/Write Access Bit 1
#define EEAR2 2 // EEPROM Read/Write Access Bit 2
#define EEAR3 3 // EEPROM Read/Write Access Bit 3
#define EEAR4 4 // EEPROM Read/Write Access Bit 4
#define EEAR5 5 // EEPROM Read/Write Access Bit 5
#define EEAR6 6 // EEPROM Read/Write Access Bit 6
#define EEAR7 7 // EEPROM Read/Write Access Bit 7
/* EEDR - EEPROM Data Register */
#define EEDR0 0 // EEPROM Data Register bit 0
#define EEDR1 1 // EEPROM Data Register bit 1
#define EEDR2 2 // EEPROM Data Register bit 2
#define EEDR3 3 // EEPROM Data Register bit 3
#define EEDR4 4 // EEPROM Data Register bit 4
#define EEDR5 5 // EEPROM Data Register bit 5
#define EEDR6 6 // EEPROM Data Register bit 6
#define EEDR7 7 // EEPROM Data Register bit 7
/* EECR - EEPROM Control Register */
#define EERE 0 // EEPROM Read Enable
#define EEPE 1 // EEPROM Write Enable
#define EEMPE 2 // EEPROM Master Write Enable
#define EERIE 3 // EEPROM Ready Interrupt Enable
#define EEPM0 4 // EEPROM Programming Mode Bit 0
#define EEPM1 5 // EEPROM Programming Mode Bit 1
/* ***** TIMER_COUNTER_0 ************** */
/* TIMSK0 - Timer/Counter0 Interrupt Mask Register */
#define TOIE0 0 // Timer/Counter0 Overflow Interrupt Enable
#define OCIE0A 1 // Timer/Counter0 Output Compare Match A Interrupt Enable
#define OCIE0B 2 // Timer/Counter0 Output Compare Match B Interrupt Enable
/* TIFR0 - Timer/Counter0 Interrupt Flag register */
#define TOV0 0 // Timer/Counter0 Overflow Flag
#define OCF0A 1 // Timer/Counter0 Output Compare Flag 0A
#define OCF0B 2 // Timer/Counter0 Output Compare Flag 0B
/* TCCR0A - Timer/Counter Control Register A */
#define WGM00 0 // Waveform Generation Mode
#define WGM01 1 // Waveform Generation Mode
#define COM0B0 4 // Compare Output Mode, Fast PWm
#define COM0B1 5 // Compare Output Mode, Fast PWm
#define COM0A0 6 // Compare Output Mode, Phase Correct PWM Mode
#define COM0A1 7 // Compare Output Mode, Phase Correct PWM Mode
/* TCCR0B - Timer/Counter Control Register B */
#define CS00 0 // Clock Select
#define CS01 1 // Clock Select
#define CS02 2 // Clock Select
#define WGM02 3 //
#define FOC0B 6 // Force Output Compare B
#define FOC0A 7 // Force Output Compare A
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