📄 mcu.h
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#define TWBR (*(volatile unsigned char *)0xB8) /* TWI Bit Rate Register */
#define TWSR (*(volatile unsigned char *)0XB9) /* TWI Status Register */
#define TWAR (*(volatile unsigned char *)0xBA) /* TWI Address Register */
#define TWDR (*(volatile unsigned char *)0xBB) /* TWI Data Register */
#define TWCR (*(volatile unsigned char *)0xBC) /* TWI Control Register */
#define UCSR0A (*(volatile unsigned char *)0xC0) /* USART0 Control and Status Register A */
#define UCSR0B (*(volatile unsigned char *)0xC1) /* USART0 Control and Status Register B */
#define UCSR0C (*(volatile unsigned char *)0xC2) /* USART0 Control and Status Register C */
#define UBRR0 (*(volatile unsigned int *)0xC4) /* USART0 Baud Rate Register */
#define UBRR0L (*(volatile unsigned char *)0xC4) /* USART0 Baud Rate Register Low */
#define UBRR0H (*(volatile unsigned char *)0xC5) /* USART0 Baud Rate Register High */
#define UDR0 (*(volatile unsigned char *)0xC6) /* USART0 I/O Data Register */
#define UCSR1A (*(volatile unsigned char *)0xC8) /* USART1 Control and Status Register A */
#define UCSR1B (*(volatile unsigned char *)0xC9) /* USART1 Control and Status Register B */
#define UCSR1C (*(volatile unsigned char *)0xCA) /* USART1 Control and Status Register C */
#define UBRR1 (*(volatile unsigned int *)0xCC) /* USART1 Baud Rate Register */
#define UBRR1L (*(volatile unsigned char *)0xCC) /* USART1 Baud Rate Register Low */
#define UBRR1H (*(volatile unsigned char *)0xCD) /* USART1 Baud Rate Register High */
#define UDR1 (*(volatile unsigned char *)0xCE) /* USART1 I/O Data Register */
/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
/* NB! vectors are specified as byte addresses */
#define RESET_vect 1
#define INT0_vect 2
#define INT1_vect 3
#define INT2_vect 4
#define INT3_vect 5
#define INT4_vect 6
#define INT5_vect 7
#define INT6_vect 8
#define INT7_vect 9
#define TIMER2_COMP_vect 10
#define TIMER2_OVF_vect 11
#define TIMER1_CAPT_vect 12
#define TIMER1_COMPA_vect 13
#define TIMER1_COMPB_vect 14
#define TIMER1_COMPC_vect 15
#define TIMER1_OVF_vect 16
#define TIMER0_COMP_vect 17
#define TIMER0_OVF_vect 18
#define CANIT_vect 19
#define CANTOVF_vect 20
#define SPI_STC_vect 21
#define USART0_RXC_vect 22
#define USART0_UDRE_vect 23
#define USART0_TXC_vect 24
#define ANA_COMP_vect 25
#define ADC_vect 26
#define EE_RDY_vect 27
#define TIMER3_CAPT_vect 28
#define TIMER3_COMPA_vect 29
#define TIMER3_COMPB_vect 30
#define TIMER3_COMPC_vect 31
#define TIMER3_OVF_vect 32
#define USART1_RXC_vect 33
#define USART1_UDRE_vect 34
#define USART1_TXC_vect 35
#define TWI_vect 36
#define SPM_RDY_vect 37
#endif /* _ICC_*/
/*==========================*/
/* Bit Position Definitions */
/*==========================*/
/* PINA : Input Pins, Port A */
#define PINA7 7
#define PINA6 6
#define PINA5 5
#define PINA4 4
#define PINA3 3
#define PINA2 2
#define PINA1 1
#define PINA0 0
/* DDRA : Data Direction Register, Port A */
#define DDA7 7
#define DDA6 6
#define DDA5 5
#define DDA4 4
#define DDA3 3
#define DDA2 2
#define DDA1 1
#define DDA0 0
/* PORTA : Data Register, Port A */
#define PORTA7 7
#define PORTA6 6
#define PORTA5 5
#define PORTA4 4
#define PORTA3 3
#define PORTA2 2
#define PORTA1 1
#define PORTA0 0
/* PORTA : Data Register, Port A */
#define PA7 7
#define PA6 6
#define PA5 5
#define PA4 4
#define PA3 3
#define PA2 2
#define PA1 1
#define PA0 0
/* PINB : Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* DDRB : Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PORTB : Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* PORTB : Data Register, Port B */
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* PINC : Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* DDRC : Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* PORTC : Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* PORTC : Data Register, Port C */
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
/* PIND : Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* DDRD : Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* PORTD : Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* PORTD : Data Register, Port D */
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* PINE : Input Pins, Port E */
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
/* DDRE : Data Direction Register, Port E */
#define DDE7 7
#define DDE6 6
#define DDE5 5
#define DDE4 4
#define DDE3 3
#define DDE2 2
#define DDE1 1
#define DDE0 0
/* PORTE : Data Register, Port E */
#define PE7 7
#define PE6 6
#define PE5 5
#define PE4 4
#define PE3 3
#define PE2 2
#define PE1 1
#define PE0 0
/* PORTE : Data Register, Port E */
#define PORTE7 7
#define PORTE6 6
#define PORTE5 5
#define PORTE4 4
#define PORTE3 3
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0
/* PINF : Input Pins, Port F */
#define PINF7 7
#define PINF6 6
#define PINF5 5
#define PINF4 4
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
/* DDRF : Data Direction Register, Port F */
#define DDF7 7
#define DDF6 6
#define DDF5 5
#define DDF4 4
#define DDF3 3
#define DDF2 2
#define DDF1 1
#define DDF0 0
/* PORTF : Data Register, Port F */
#define PF7 7
#define PF6 6
#define PF5 5
#define PF4 4
#define PF3 3
#define PF2 2
#define PF1 1
#define PF0 0
/* PORTF : Data Register, Port F */
#define PORTF7 7
#define PORTF6 6
#define PORTF5 5
#define PORTF4 4
#define PORTF3 3
#define PORTF2 2
#define PORTF1 1
#define PORTF0 0
/* Input Pins, Port G */
#define PING4 4
#define PING3 3
#define PING2 2
#define PING1 1
#define PING0 0
/* DDRG : Data Direction Register, Port G */
#define DDG4 4
#define DDG3 3
#define DDG2 2
#define DDG1 1
#define DDG0 0
/* PORTG : Data Register, Port G */
#define PG4 4
#define PG3 3
#define PG2 2
#define PG1 1
#define PG0 0
/* PORTG : Data Register, Port G */
#define PORTG4 4
#define PORTG3 3
#define PORTG2 2
#define PORTG1 1
#define PORTG0 0
/* TFR0 : Timer/Counter Interrupt Flag Register 0 */
#define OCF0A 1
#define TOV0 0
/* TFR1 : Timer/Counter Interrupt Flag Register 1 */
#define ICF1 5
#define OCF1C 3
#define OCF1B 2
#define OCF1A 1
#define TOV1 0
/* TFR2 : Timer/Counter Interrupt Flag Register 2 */
#define OCF2A 1
#define TOV2 0
/* TFR3 : Timer/Counter Interrupt Flag Register 3 */
#define ICF3 5
#define OCF3C 3
#define OCF3B 2
#define OCF3A 1
#define TOV3 0
/* EIFR : External Interrupt Flag Register */
#define INTF7 7
#define INTF6 6
#define INTF5 5
#define INTF4 4
#define INTF3 3
#define INTF2 2
#define INTF1 1
#define INTF0 0
/* EIMSK : External Interrupt Mask Register */
#define INT7 7
#define INT6 6
#define INT5 5
#define INT4 4
#define INT3 3
#define INT2 2
#define INT1 1
#define INT0 0
/* EICRA : External Interrupt Control Register A*/
#define ISC31 7
#define ISC30 6
#define ISC21 5
#define ISC20 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* EICRA : External Interrupt Control Register B*/
#define ISC71 7
#define ISC70 6
#define ISC61 5
#define ISC60 4
#define ISC51 3
#define ISC50 2
#define ISC41 1
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