gate.spj

来自「几个简单的verilog代码」· SPJ 代码 · 共 73 行

[Settings]
Mode=Debug
SimFile=
busFile=
TabStop=4
Version=97.1
[Explorer]
P1Width=261
P2Width=321
View=List
C1Width=144
C2Width=144
Scope=stimulus.vendY
[Browser]
Scope=stimulus
[DebugMode]
Delay=Typ
SaveAll=Yes
SaveCell=Yes
SilosExt=No
LogFile=No
FunctionalSim=No
RetainSimData=No
DiskSize=1000M
CommandLine=
[Analyzer]
SymbolFile=
C1Width=118
C2Width=90
C3Width=60
P1Width=270
P2Width=431
[Files]
0=vendtest.v
1=vend.gv

[LibraryFiles]
0=abc_100.v

[Options]
AutoFileSave=Yes
DebugEnable=No
CCEnable=No
CcOpEnable=No
[Position]
Width=875
Height=668
X=33
Y=61
[Group0]
Name=Default
0=stimulus : reset
1=stimulus : newspaper
2=stimulus : coin[1:0]
3=stimulus : clock

[Group1]
Name=vending
0=stimulus:reset
1=stimulus:newspaper
2=stimulus:coin[1:0]
3=stimulus:clock



[WindowPos]
Output=0,1,0,-1,0,-1,0,0,720,319
OpenWindows=1
Analyzer=0,1,0,-1,0,-1,22,22,742,341

[GroupList]
0=Default