start_v2.lst

keil下开发的永磁同步电机矢量控制程序

 0001                     400     _BYTDIS EQU 1 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          401                             ; 1 = BHE disabled (GPIO function if implemented)
                          402     ;
A166 MACRO ASSEMBLER  START_V2                                                            12/19/2003 11:51:09 PAGE     8

                          403     ; ALEDIS: ALE pin disable (EBCMOD0.13)
 0001                     404     _ALEDIS EQU 1 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          405                             ; 1 = ALE pin disabled (GPIO function if implemented)
                          406     ;
                          407     ; RDYDIS: READY pin disable (EBCMOD0.14)
 0001                     408     _RDYDIS EQU 1 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          409                             ; 1 = READY disabled (GPIO function if implemented)
                          410     ;
                          411     ; RDYPOL: READY pin polarity (EBCMOD0.15)
 0000                     412     _RDYPOL EQU 0 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          413                             ; 1 = READY pin is active high
                          414     ;
                          415     ;
                          416     ;
                          417     ; Definitions for EBC Mode 1 register EBCMOD1
                          418     ; ===========================================
                          419     ;
                          420     ; APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD0.4)
 001F                     421     _APDIS EQU 31 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          422                             ; 1 - 30 = reserved
                          423                             ; 31 = Address bus disabled (PORT1 used as GPIO)
                          424     ;
                          425     ; DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
 0001                     426     _DHPDIS EQU 1 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          427                             ; 1 = Data bus pins 15-8 disabled (used as GPIO)
                          428     ;
                          429     ;
                          430     ;
                          431     ; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS0 AREA ===========
                          432     ;
                          433     ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
                          434     $SET (CONFIG_CS0 = 1) ; Uv2/Dave /Dave/                                               
                                                                                                                 
                          435     ;
                          436     ; Definitions for Function Configuration Register FCONCS0
                          437     ; =======================================================
                          438     ;
                          439     ; ENCS0: Enable Chip Select (FCONCS0.0)
 0000                     440     _ENCS0 EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          441                             ; 1 = Chip Select 0 enabled
                          442     ;
                          443     ; RDYEN0: Ready Enable (FCONCS0.1)
 0000                     444     _RDYEN0 EQU 0 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          445                             ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
                          446     ;
                          447     ; RDYMOD0: Ready Mode (FCONCS0.2)
 0000                     448     _RDYMOD0 EQU 0 ; Uv2/Dave /Dave/                                                      
                                                                                                          
                          449                             ; 1 = Synchronous READY
                          450     ;
                          451     ; BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
 0000                     452     _BTYP0 EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          453                             ; 1 = 8 bit Multiplexed bus
                          454                             ; 2 = 16 bit Demultiplexed bus
                          455                             ; 3 = 16 bit Multiplexed bus
                          456     ;
                          457     ;
                          458     ; TCONCS0: Definitions for the Timing Configuration register 
A166 MACRO ASSEMBLER  START_V2                                                            12/19/2003 11:51:09 PAGE     9

                          459     ; ==========================================================
                          460     ;
                          461     ; PHA0: Phase A clock cycle (TCONCS0.0 .. TCONCS0.1)
 0003                     462     _PHA0 EQU 3 ; Uv2/Dave /Dave/                                                         
                                                                                                       
                          463                             ; : = : 
                          464                             ; 3 = 3 clock cycles
                          465     ;
                          466     ; PHB0: Phase B clock cycle (TCONCS0.2)
 0000                     467     _PHB0 EQU 0 ; Uv2/Dave /Dave/                                                         
                                                                                                       
                          468                             ; 1 = 2 clock cycles
                          469     ;
                          470     ; PHC0: Phase C clock cycle (TCONCS0.3 .. TCONCS0.4)
 0000                     471     _PHC0 EQU 0 ; Uv2/Dave /Dave/                                                         
                                                                                                       
                          472                             ; : = :
                          473                             ; 3 = 3 clock cycles
                          474     ;
                          475     ; PHD0: Phase D clock cycle (TCONCS0.5)
 0000                     476     _PHD0 EQU 0 ; Uv2/Dave /Dave/                                                         
                                                                                                       
                          477                             ; 1 = 1 clock cycle
                          478     ;
                          479     ; PHE0: Phase E clock cycle (TCONCS0.6 .. TCONCS0.10)
 0009                     480     _PHE0 EQU 9 ; Uv2/Dave /Dave/                                                         
                                                                                                       
                          481                             ; : = :
                          482                             ; 31 = 32 clock cycles
                          483     ;
                          484     ; RDPHF0: Phase F read clock cycle (TCONCS0.11 .. TCONCS0.12)
 0000                     485     _RDPHF0 EQU 0 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          486                             ; : = :
                          487                             ; 3 = 3 clock cycles
                          488     ;
                          489     ; WRPHF0: Phase F write clock cycle (TCONCS0.13 .. TCONCS0.14)
 0003                     490     _WRPHF0 EQU 3 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          491                             ; : = :
                          492                             ; 3 = 3 clock cycles
                          493     ;
                          494     ;
                          495     ; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS1 AREA ===========
                          496     ;
                          497     ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
                          498     $SET (CONFIG_CS1 = 0) ; Uv2/Dave /Dave/                                               
                                                                                                                 
                          499     ;
                          500     ; Definitions for Address Select register ADDRSEL1
                          501     ; ================================================
                          502     ;
 0000                     503     _ADDR1 EQU 0x0 ; Uv2/Dave /Dave/                                                      
                                                                                                          
                          504     ;
 1000                     505     _SIZE1 EQU 4*KB ; Uv2/Dave /Dave/                                                     
                                                                                                           
                          506                                  ; possible values for _SIZE1 are:
                          507                                  ;    4*KB            (gives RGSZ1 = 0)
                          508                                  ;    8*KB            (gives RGSZ1 = 1)
                          509                                  ;   16*KB            (gives RGSZ1 = 2)
                          510                                  ;   32*KB            (gives RGSZ1 = 3)
                          511                                  ;   64*KB            (gives RGSZ1 = 4)
                          512                                  ;  128*KB            (gives RGSZ1 = 5)
                          513                                  ;  256*KB            (gives RGSZ1 = 6)
                          514                                  ;  512*KB            (gives RGSZ1 = 7)
A166 MACRO ASSEMBLER  START_V2                                                            12/19/2003 11:51:09 PAGE    10

                          515                                  ; 1024*KB  or  1*MB  (gives RGSZ1 = 8)
                          516                                  ; 2048*KB  or  2*MB  (gives RGSZ1 = 9)
                          517                                  ; 4096*KB  or  4*MB  (gives RGSZ1 = 10)
                          518                                  ; 8192*KB  or  8*MB  (gives RGSZ1 = 11)
                          519                                  ;                    (RGSZ1 = 12 .. 15 reserved)
                          520     ;
                          521     ; Definitions for Function Configuration Register FCONCS1
                          522     ; =======================================================
                          523     ;
                          524     ; ENCS1: Enable Chip Select (FCONCS1.0)
 0000                     525     _ENCS1 EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          526                             ; 1 = Chip Select 0 enabled
                          527     ;
                          528     ; RDYEN1: Ready Enable (FCONCS1.1)