start_v2.lst

keil下开发的永磁同步电机矢量控制程序

                          266                             ; 1 = RSTOUT pin operates as GPIO
                          267     ;
                          268     ; ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
 0000                     269     _ROCOFF EQU 0 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          270                             ; 1 = RSTOUT is deactiveted at end of reset
                          271     ;
                          272     ; ROCON: RSTOUT# Control Switch Off (RSTCON.6)
 0000                     273     _ROCON EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          274                             ; 1 = RSTOUT is only activated upon a hardware reset
                          275     ;
                          276     ; RODIS: RSTOUT# Disable Control (RSTCON.7)
 0000                     277     _RODIS EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          278                             ; 1 = RSTOUT is deactivated
                          279     ;
                          280     ;
                          281     ;
                          282     ; Definitions for PLL Control Register PLLCON
                          283     ; ===========================================
                          284     ;
                          285     ; INIT_PLLCON: Init PLLCON register
                          286     ; --- Set INIT_PLLCON = 1 to initilize the PLLCON register
                          287     $SET (INIT_PLLCON = 1)
A166 MACRO ASSEMBLER  START_V2                                                            12/19/2003 11:51:09 PAGE     6

                          288     ;
                          289     ; PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3)
 0009                     290     _PLLODIV  EQU    9      ; 0 .. 14  Fpll = Fvco / (PLLODIV+1)
                          291                             ; 15 = reserved
                          292     ;
                          293     ; PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5)
 0000                     294     _PLLIDIV  EQU    0      ; 0 .. 3   Fin = Fosc / (PLLIDIV+1)
                          295     ;
                          296     ; PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
 0002                     297     _PLLVB    EQU    2      ; ValueVCO output frequency    Base frequency
                          298                             ; 0 = 100...150 MHz            20...80 MHz
                          299                             ; 1 = 150...200 MHz            40...130 MHz
                          300                             ; 2 = 200...250 MHz [def.]     60...180 MHz
                          301                             ; 3 = (250...300 MHz) Reserved
                          302     ;
                          303     ; PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12)
 0018                     304     _PLLMUL   EQU    24     ; 7 .. 31  Fvco = Fin * (PLLMUL+1)
                          305                             ; 0 .. 6 = reserved
                          306     ;
                          307     ; PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
 0003                     308     _PLLCTRL  EQU    3      ; 0 = Bypass PLL clock mult., the VCO is off
                          309                             ; 1 = Bypass PLL clock mult., the VCO is running
                          310                             ; 2 = VCO clock used, input clock switched off
                          311                             ; 3 = VCO clock used, input clock connected
                          312     ;
                          313     ; PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
 0000                     314     _PLLWRI   EQU    0      ; 0 = Register PLLCON may be written
                          315                             ; 1 = Write cycles to register PLLCON are ignored
                          316     ;
                          317     ;
                          318     ; Definitions for Watchdog Timer Control Register WDTCON
                          319     ; ======================================================
                          320     ;
                          321     ; --- Set WATCHDOG = 1 to enable the Hardware watchdog and initilize the WDTCON regist
                                  er
                          322     $SET (WATCHDOG = 0) ; Uv2/Dave /Dave/                                                 
                                                                                                               
                          323     ;
                          324     ; WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
 0000                     325     _WDTIN EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          326                             ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
                          327                             ; 2 = frequency f_peripheral / 4
                          328                             ; 3 = frequency f_peripheral / 256
                          329     ;
                          330     ; WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15)
 0000                     331     _WDTREL EQU 0 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          332     ;
                          333     ;
                          334     ; Definitions for Frequency Output Signal FOCON
                          335     ; =============================================
                          336     ;
                          337     ; INIT_FOCON: Init FOCON register
                          338     ; --- Set INIT_FOCON = 1 to initilize the FOCON register
                          339     $SET (INIT_FOCON = 1) ; Uv2/Dave /Dave/                                               
                                                                                                                 
                          340     ;
                          341     ; CLKEN: CLKOUT Enable (FOCON.7)
 0000                     342     _CLKEN EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          343                             ; 1 = P3.15 outputs signal CLKOUT
                          344     ;
                          345     ; FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13)
 0003                     346     _FORV EQU 3 ; Uv2/Dave /Dave/                                                         
                                                                                                       
A166 MACRO ASSEMBLER  START_V2                                                            12/19/2003 11:51:09 PAGE     7

                          347     ;
                          348     ; FOSS: Frequency Output Signal Select (FOCON.14)
 0000                     349     _FOSS EQU 0 ; Uv2/Dave /Dave/                                                         
                                                                                                       
                          350                             ; 1 = Output of reload counter; duty cycle depends on FORV
                          351     ;
                          352     ; FOEN: Frequency Output Enable (FOCON.15)
 0000                     353     _FOEN EQU 0 ; Uv2/Dave /Dave/                                                         
                                                                                                       
                          354                             ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
                          355     ;
                          356     ;
                          357     ; ============= CONFIGURE EXTERNAL BUS (EBC) BEHAVIOUR =====================
                          358     ;
                          359     ; --- Set CONFIG_EBC = 1 to initialize the EBCMOD0/EBCMOD1 registers
                          360     $SET (CONFIG_EBC = 1) ; Uv2/Dave /Dave/                                               
                                                                                                                 
                          361                             ;     of configuration bus (typical Port0) values.
                          362                             ; 1 = the following external bus configuration values
                          363                             ;      are written to EBCMOD and BUSACT0
                          364     ;
                          365     ; Definitions for EBC Mode 0 register EBCMOD0
                          366     ; ===========================================
                          367     ;
                          368     ; SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3)
 0002                     369     _SAPEN EQU 2 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          370                             ; 1 = One (A16) segment address pin enabled
                          371                             ; : = :        
                          372                             ; 8 = Eight (A16 .. A23) address pins enabled
                          373                             ; 9 - 15 = reserved
                          374     ;
                          375     ; CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7)
 0003                     376     _CSPEN EQU 3 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          377                             ; 1 = One CS (CS0) pin enabled
                          378                             ; : = :
                          379                             ; 8 = Eight CS (CS0 .. CS7) pins enabled
                          380                             ; 9 - 15 = reserved
                          381     ; Note: the number of available CS pins depends on the chip used
                          382     ;
                          383     ; ARBEN: Bus Arbitration Pins Enabled (EBCMOD0.8)
 0000                     384     _ARBEN EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          385                             ; 1 = HOLD, HLDA and BREQ pins act normally
                          386     ;
                          387     ; SLAVE: SLAVE mode enable (EBCMOD0.9)
 0000                     388     _SLAVE EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          389                             ; 1 = Bus arbiter acts in slave mode
                          390     ;
                          391     ; EBCDIS: EBC pins disable (EBCMOD0.10)
 0001                     392     _EBCDIS EQU 1 ; Uv2/Dave /Dave/                                                       
                                                                                                         
                          393                             ; 1 = EBC off (pins to be used as GPIO if implemented)
                          394     ;
                          395     ; WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
 0000                     396     _WRCFG EQU 0 ; Uv2/Dave /Dave/                                                        
                                                                                                        
                          397                             ; 1 = Pins act as WRL and WRH
                          398     ;
                          399     ; BYTDIS: BHE pin disable (EBCMOD0.12)