📄 start_v2.a66
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_ADDR6 EQU 0x0 ; Uv2/Dave /Dave/
;
_SIZE6 EQU 4*KB ; Uv2/Dave /Dave/
; possible values for _SIZE6 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS6
; =======================================================
;
; ENCS6: Enable Chip Select (FCONCS6.0)
_ENCS6 EQU 0 ; Uv2/Dave /Dave/
; 1 = Chip Select 0 enabled
;
; RDYEN6: Ready Enable (FCONCS6.1)
_RDYEN6 EQU 0 ; Uv2/Dave /Dave/
; 1 = Access time cont. by TCONCS6.PHE6 and READY signal
;
; RDYMOD6: Ready Mode (FCONCS6.2)
_RDYMOD6 EQU 0 ; Uv2/Dave /Dave/
; 1 = Synchronous READY
;
; BTYP6: Bus Type Selection (FCONCS6.4 .. FCONCS6.5)
_BTYP6 EQU 0 ; Uv2/Dave /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS6: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA6: Phase A clock cycle (TCONCS6.0 .. TCONCS6.1)
_PHA6 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHB6: Phase B clock cycle (TCONCS6.2)
_PHB6 EQU 0 ; Uv2/Dave /Dave/
; 1 = 2 clock cycles
;
; PHC6: Phase C clock cycle (TCONCS6.3 .. TCONCS6.4)
_PHC6 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHD6: Phase D clock cycle (TCONCS6.5)
_PHD6 EQU 0 ; Uv2/Dave /Dave/
; 1 = 1 clock cycle
;
; PHE6: Phase E clock cycle (TCONCS6.6 .. TCONCS6.10)
_PHE6 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 31 = 32 clock cycles
;
; RDPHF6: Phase F read clock cycle (TCONCS6.11 .. TCONCS6.12)
_RDPHF6 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; WRPHF6: Phase F write clock cycle (TCONCS6.13 .. TCONCS6.14)
_WRPHF6 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS7 AREA ===========
;
; --- Set CONFIG_CS7 = 1 to initialize the ADDRSEL7/FCONCS7/TCONCS7 registers
; --- Note: The CS7# chip default at reset allows to access the on-chip Twin-CAN
$SET (CONFIG_CS7 = 0) ; Uv2/Dave /Dave/
;
; Definitions for Address Select register ADDRSEL7
; ================================================
;
_ADDR7 EQU 0x0 ; Uv2/Dave /Dave/
;
_SIZE7 EQU 4*KB ; Uv2/Dave /Dave/
; possible values for _SIZE7 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS7
; =======================================================
;
; ENCS7: Enable Chip Select (FCONCS7.0)
_ENCS7 EQU 0 ; Uv2/Dave /Dave/
; 1 = Chip Select 0 enabled
;
; RDYEN7: Ready Enable (FCONCS7.1)
_RDYEN7 EQU 0 ; Uv2/Dave /Dave/
; 1 = Access time cont. by TCONCS7.PHE7 and READY signal
;
; RDYMOD7: Ready Mode (FCONCS7.2)
_RDYMOD7 EQU 0 ; Uv2/Dave /Dave/
; 1 = Synchronous READY
;
; BTYP7: Bus Type Selection (FCONCS7.4 .. FCONCS7.5)
_BTYP7 EQU 0 ; Uv2/Dave /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS7: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA7: Phase A clock cycle (TCONCS7.0 .. TCONCS7.1)
_PHA7 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHB7: Phase B clock cycle (TCONCS7.2)
_PHB7 EQU 0 ; Uv2/Dave /Dave/
; 1 = 2 clock cycles
;
; PHC7: Phase C clock cycle (TCONCS7.3 .. TCONCS7.4)
_PHC7 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHD7: Phase D clock cycle (TCONCS7.5)
_PHD7 EQU 0 ; Uv2/Dave /Dave/
; 1 = 1 clock cycle
;
; PHE7: Phase E clock cycle (TCONCS7.6 .. TCONCS7.10)
_PHE7 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 31 = 32 clock cycles
;
; RDPHF7: Phase F read clock cycle (TCONCS7.11 .. TCONCS7.12)
_RDPHF7 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; WRPHF7: Phase F write clock cycle (TCONCS7.13 .. TCONCS7.14)
_WRPHF7 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
;------------------------------------------------------------------------------
$IF TINY
$SET (DPPUSE = 0)
$ENDIF
$IF NOT TINY
ASSUME DPP3:SYSTEM
ASSUME DPP2:NDATA
$ENDIF
NAME ?C_STARTUP
PUBLIC ?C_STARTUP
PUBLIC ?L?VECSC
?L?VECSC EQU _VECSC ; Interrupt Vector Spacing for L166
$IF MEDIUM OR LARGE OR HLARGE
Model LIT 'FAR'
$ELSE
Model LIT 'NEAR'
$ENDIF
EXTRN main:Model
PUBLIC ?C_USRSTKBOT
?C_USERSTACK SECTION DATA PUBLIC 'NDATA'
$IF NOT TINY
NDATA DGROUP ?C_USERSTACK
$ENDIF
?C_USRSTKBOT:
DS USTSZ ; Size of User Stack
?C_USERSTKTOP:
?C_USERSTACK ENDS
IF UST1SZ ; Define User Stack 1 area
?C_USERSTACK1 SECTION DATA PUBLIC 'NDATA'
$IF NOT TINY
NDATA DGROUP ?C_USERSTACK
$ENDIF
?C_USRSTKBOT1:
DS UST1SZ ; Size of User Stack 1
?C_USERSTKTOP1:
?C_USERSTACK1 ENDS
ENDIF
IF UST2SZ ; Define User Stack 2 area
?C_USERSTACK2 SECTION DATA PUBLIC 'NDATA'
$IF NOT TINY
NDATA DGROUP ?C_USERSTACK
$ENDIF
?C_USRSTKBOT2:
DS UST2SZ ; Size of User Stack 2
?C_USERSTKTOP2:
?C_USERSTACK2 ENDS
ENDIF
?C_MAINREGISTERS REGDEF R0 - R15
?C⌨️ 快捷键说明
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