📄 start_v2.a66
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; RDYEN3: Ready Enable (FCONCS3.1)
_RDYEN3 EQU 0 ; Uv2/Dave /Dave/
; 1 = Access time cont. by TCONCS3.PHE3 and READY signal
;
; RDYMOD3: Ready Mode (FCONCS3.2)
_RDYMOD3 EQU 0 ; Uv2/Dave /Dave/
; 1 = Synchronous READY
;
; BTYP3: Bus Type Selection (FCONCS3.4 .. FCONCS3.5)
_BTYP3 EQU 0 ; Uv2/Dave /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS3: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA3: Phase A clock cycle (TCONCS3.0 .. TCONCS3.1)
_PHA3 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHB3: Phase B clock cycle (TCONCS3.2)
_PHB3 EQU 0 ; Uv2/Dave /Dave/
; 1 = 2 clock cycles
;
; PHC3: Phase C clock cycle (TCONCS3.3 .. TCONCS3.4)
_PHC3 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHD3: Phase D clock cycle (TCONCS3.5)
_PHD3 EQU 0 ; Uv2/Dave /Dave/
; 1 = 1 clock cycle
;
; PHE3: Phase E clock cycle (TCONCS3.6 .. TCONCS3.10)
_PHE3 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 31 = 32 clock cycles
;
; RDPHF3: Phase F read clock cycle (TCONCS3.11 .. TCONCS3.12)
_RDPHF3 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; WRPHF3: Phase F write clock cycle (TCONCS3.13 .. TCONCS3.14)
_WRPHF3 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS4 AREA ===========
;
; --- Set CONFIG_CS4 = 1 to initialize the ADDRSEL4/FCONCS4/TCONCS4 registers
$SET (CONFIG_CS4 = 0) ; Uv2/Dave /Dave/
;
; Definitions for Address Select register ADDRSEL4
; ================================================
;
_ADDR4 EQU 0x0 ; Uv2/Dave /Dave/
;
_SIZE4 EQU 4*KB ; Uv2/Dave /Dave/
; possible values for _SIZE4 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS4
; =======================================================
;
; ENCS4: Enable Chip Select (FCONCS4.0)
_ENCS4 EQU 0 ; Uv2/Dave /Dave/
; 1 = Chip Select 0 enabled
;
; RDYEN4: Ready Enable (FCONCS4.1)
_RDYEN4 EQU 0 ; Uv2/Dave /Dave/
; 1 = Access time cont. by TCONCS4.PHE4 and READY signal
;
; RDYMOD4: Ready Mode (FCONCS4.2)
_RDYMOD4 EQU 0 ; Uv2/Dave /Dave/
; 1 = Synchronous READY
;
; BTYP4: Bus Type Selection (FCONCS4.4 .. FCONCS4.5)
_BTYP4 EQU 0 ; Uv2/Dave /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS4: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA4: Phase A clock cycle (TCONCS4.0 .. TCONCS4.1)
_PHA4 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHB4: Phase B clock cycle (TCONCS4.2)
_PHB4 EQU 0 ; Uv2/Dave /Dave/
; 1 = 2 clock cycles
;
; PHC4: Phase C clock cycle (TCONCS4.3 .. TCONCS4.4)
_PHC4 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHD4: Phase D clock cycle (TCONCS4.5)
_PHD4 EQU 0 ; Uv2/Dave /Dave/
; 1 = 1 clock cycle
;
; PHE4: Phase E clock cycle (TCONCS4.6 .. TCONCS4.10)
_PHE4 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 31 = 32 clock cycles
;
; RDPHF4: Phase F read clock cycle (TCONCS4.11 .. TCONCS4.12)
_RDPHF4 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; WRPHF4: Phase F write clock cycle (TCONCS4.13 .. TCONCS4.14)
_WRPHF4 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS5 AREA ===========
;
; --- Set CONFIG_CS5 = 1 to initialize the ADDRSEL5/FCONCS5/TCONCS5 registers
$SET (CONFIG_CS5 = 0) ; Uv2/Dave /Dave/
;
; Definitions for Address Select register ADDRSEL5
; ================================================
;
_ADDR5 EQU 0x0 ; Uv2/Dave /Dave/
;
_SIZE5 EQU 4*KB ; Uv2/Dave /Dave/
; possible values for _SIZE5 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS5
; =======================================================
;
; ENCS5: Enable Chip Select (FCONCS5.0)
_ENCS5 EQU 0 ; Uv2/Dave /Dave/
; 1 = Chip Select 0 enabled
;
; RDYEN5: Ready Enable (FCONCS5.1)
_RDYEN5 EQU 0 ; Uv2/Dave /Dave/
; 1 = Access time cont. by TCONCS5.PHE5 and READY signal
;
; RDYMOD5: Ready Mode (FCONCS5.2)
_RDYMOD5 EQU 0 ; Uv2/Dave /Dave/
; 1 = Synchronous READY
;
; BTYP5: Bus Type Selection (FCONCS5.4 .. FCONCS5.5)
_BTYP5 EQU 0 ; Uv2/Dave /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS5: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA5: Phase A clock cycle (TCONCS5.0 .. TCONCS5.1)
_PHA5 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHB5: Phase B clock cycle (TCONCS5.2)
_PHB5 EQU 0 ; Uv2/Dave /Dave/
; 1 = 2 clock cycles
;
; PHC5: Phase C clock cycle (TCONCS5.3 .. TCONCS5.4)
_PHC5 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHD5: Phase D clock cycle (TCONCS5.5)
_PHD5 EQU 0 ; Uv2/Dave /Dave/
; 1 = 1 clock cycle
;
; PHE5: Phase E clock cycle (TCONCS5.6 .. TCONCS5.10)
_PHE5 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 31 = 32 clock cycles
;
; RDPHF5: Phase F read clock cycle (TCONCS5.11 .. TCONCS5.12)
_RDPHF5 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; WRPHF5: Phase F write clock cycle (TCONCS5.13 .. TCONCS5.14)
_WRPHF5 EQU 0 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS6 AREA ===========
;
; --- Set CONFIG_CS6 = 1 to initialize the ADDRSEL6/FCONCS6/TCONCS6 registers
$SET (CONFIG_CS6 = 0) ; Uv2/Dave /Dave/
;
; Definitions for Address Select register ADDRSEL6
; ================================================
;
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