📄 start_v2.a66
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CC1DIS EQU 0 ; Uv2/Dave /Dave/
CC2DIS EQU 1 ; Uv2/Dave /Dave/
CC6DIS EQU 0 ; Uv2/Dave /Dave/
; reserved (SYSCON3.9)
ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10)
I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11)
SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12)
CANDIS EQU 0 ; Uv2/Dave /Dave/
; reserved (SYSCON3.14)
SSC1DIS EQU 1 ; Uv2/Dave /Dave/
;
;
;
; Definitions for Reset Configuration Register RSTCON
; ===================================================
;
; INIT_RSTCON: Init RSTCON register
; --- Set INIT_RSTCON = 1 to initilize the RSTCON register
$SET (INIT_RSTCON = 0) ; Uv2/Dave /Dave/
;
; RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
_RSTLEN EQU 0 ; Uv2/Dave /Dave/
; 1 = 4 t_CPU clocks
; 2 = 8 t_CPU clocks
; 3 = 16 t_CPU clocks
; 4 = 32 t_CPU clocks
; 5 = 64 t_CPU clocks
; 6 = 128 t_CPU clocks
; 7 = 256 t_CPU clocks
;
; RORMV: RSTOUT# Remove Control (RSTCON.4)
_RORMV EQU 0 ; Uv2/Dave /Dave/
; 1 = RSTOUT pin operates as GPIO
;
; ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
_ROCOFF EQU 0 ; Uv2/Dave /Dave/
; 1 = RSTOUT is deactiveted at end of reset
;
; ROCON: RSTOUT# Control Switch Off (RSTCON.6)
_ROCON EQU 0 ; Uv2/Dave /Dave/
; 1 = RSTOUT is only activated upon a hardware reset
;
; RODIS: RSTOUT# Disable Control (RSTCON.7)
_RODIS EQU 0 ; Uv2/Dave /Dave/
; 1 = RSTOUT is deactivated
;
;
;
; Definitions for PLL Control Register PLLCON
; ===========================================
;
; INIT_PLLCON: Init PLLCON register
; --- Set INIT_PLLCON = 1 to initilize the PLLCON register
$SET (INIT_PLLCON = 1)
;
; PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3)
_PLLODIV EQU 9 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1)
; 15 = reserved
;
; PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5)
_PLLIDIV EQU 0 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1)
;
; PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
_PLLVB EQU 2 ; ValueVCO output frequency Base frequency
; 0 = 100...150 MHz 20...80 MHz
; 1 = 150...200 MHz 40...130 MHz
; 2 = 200...250 MHz [def.] 60...180 MHz
; 3 = (250...300 MHz) Reserved
;
; PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12)
_PLLMUL EQU 24 ; 7 .. 31 Fvco = Fin * (PLLMUL+1)
; 0 .. 6 = reserved
;
; PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
_PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off
; 1 = Bypass PLL clock mult., the VCO is running
; 2 = VCO clock used, input clock switched off
; 3 = VCO clock used, input clock connected
;
; PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
_PLLWRI EQU 0 ; 0 = Register PLLCON may be written
; 1 = Write cycles to register PLLCON are ignored
;
;
; Definitions for Watchdog Timer Control Register WDTCON
; ======================================================
;
; --- Set WATCHDOG = 1 to enable the Hardware watchdog and initilize the WDTCON register
$SET (WATCHDOG = 0) ; Uv2/Dave /Dave/
;
; WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
_WDTIN EQU 0 ; Uv2/Dave /Dave/
; 1 = frequency f_peripheral / 128 (recommended for START_V2)
; 2 = frequency f_peripheral / 4
; 3 = frequency f_peripheral / 256
;
; WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15)
_WDTREL EQU 0 ; Uv2/Dave /Dave/
;
;
; Definitions for Frequency Output Signal FOCON
; =============================================
;
; INIT_FOCON: Init FOCON register
; --- Set INIT_FOCON = 1 to initilize the FOCON register
$SET (INIT_FOCON = 1) ; Uv2/Dave /Dave/
;
; CLKEN: CLKOUT Enable (FOCON.7)
_CLKEN EQU 0 ; Uv2/Dave /Dave/
; 1 = P3.15 outputs signal CLKOUT
;
; FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13)
_FORV EQU 3 ; Uv2/Dave /Dave/
;
; FOSS: Frequency Output Signal Select (FOCON.14)
_FOSS EQU 0 ; Uv2/Dave /Dave/
; 1 = Output of reload counter; duty cycle depends on FORV
;
; FOEN: Frequency Output Enable (FOCON.15)
_FOEN EQU 0 ; Uv2/Dave /Dave/
; 1 = P3.15 outputs f_OUT when _CLKEN is 0
;
;
; ============= CONFIGURE EXTERNAL BUS (EBC) BEHAVIOUR =====================
;
; --- Set CONFIG_EBC = 1 to initialize the EBCMOD0/EBCMOD1 registers
$SET (CONFIG_EBC = 1) ; Uv2/Dave /Dave/
; of configuration bus (typical Port0) values.
; 1 = the following external bus configuration values
; are written to EBCMOD and BUSACT0
;
; Definitions for EBC Mode 0 register EBCMOD0
; ===========================================
;
; SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3)
_SAPEN EQU 2 ; Uv2/Dave /Dave/
; 1 = One (A16) segment address pin enabled
; : = :
; 8 = Eight (A16 .. A23) address pins enabled
; 9 - 15 = reserved
;
; CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7)
_CSPEN EQU 3 ; Uv2/Dave /Dave/
; 1 = One CS (CS0) pin enabled
; : = :
; 8 = Eight CS (CS0 .. CS7) pins enabled
; 9 - 15 = reserved
; Note: the number of available CS pins depends on the chip used
;
; ARBEN: Bus Arbitration Pins Enabled (EBCMOD0.8)
_ARBEN EQU 0 ; Uv2/Dave /Dave/
; 1 = HOLD, HLDA and BREQ pins act normally
;
; SLAVE: SLAVE mode enable (EBCMOD0.9)
_SLAVE EQU 0 ; Uv2/Dave /Dave/
; 1 = Bus arbiter acts in slave mode
;
; EBCDIS: EBC pins disable (EBCMOD0.10)
_EBCDIS EQU 1 ; Uv2/Dave /Dave/
; 1 = EBC off (pins to be used as GPIO if implemented)
;
; WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
_WRCFG EQU 0 ; Uv2/Dave /Dave/
; 1 = Pins act as WRL and WRH
;
; BYTDIS: BHE pin disable (EBCMOD0.12)
_BYTDIS EQU 1 ; Uv2/Dave /Dave/
; 1 = BHE disabled (GPIO function if implemented)
;
; ALEDIS: ALE pin disable (EBCMOD0.13)
_ALEDIS EQU 1 ; Uv2/Dave /Dave/
; 1 = ALE pin disabled (GPIO function if implemented)
;
; RDYDIS: READY pin disable (EBCMOD0.14)
_RDYDIS EQU 1 ; Uv2/Dave /Dave/
; 1 = READY disabled (GPIO function if implemented)
;
; RDYPOL: READY pin polarity (EBCMOD0.15)
_RDYPOL EQU 0 ; Uv2/Dave /Dave/
; 1 = READY pin is active high
;
;
;
; Definitions for EBC Mode 1 register EBCMOD1
; ===========================================
;
; APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD0.4)
_APDIS EQU 31 ; Uv2/Dave /Dave/
; 1 - 30 = reserved
; 31 = Address bus disabled (PORT1 used as GPIO)
;
; DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
_DHPDIS EQU 1 ; Uv2/Dave /Dave/
; 1 = Data bus pins 15-8 disabled (used as GPIO)
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS0 AREA ===========
;
; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
$SET (CONFIG_CS0 = 1) ; Uv2/Dave /Dave/
;
; Definitions for Function Configuration Register FCONCS0
; =======================================================
;
; ENCS0: Enable Chip Select (FCONCS0.0)
_ENCS0 EQU 0 ; Uv2/Dave /Dave/
; 1 = Chip Select 0 enabled
;
; RDYEN0: Ready Enable (FCONCS0.1)
_RDYEN0 EQU 0 ; Uv2/Dave /Dave/
; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
;
; RDYMOD0: Ready Mode (FCONCS0.2)
_RDYMOD0 EQU 0 ; Uv2/Dave /Dave/
; 1 = Synchronous READY
;
; BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
_BTYP0 EQU 0 ; Uv2/Dave /Dave/
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS0: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA0: Phase A clock cycle (TCONCS0.0 .. TCONCS0.1)
_PHA0 EQU 3 ; Uv2/Dave /Dave/
; : = :
; 3 = 3 clock cycles
;
; PHB0: Phase B clock cycle (TCONCS0.2)
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