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📄 start_v2.a66

📁 keil下开发的永磁同步电机矢量控制程序
💻 A66
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$MODV2                                  ; Define C166v2 core mode
;
;------------------------------------------------------------------------------
;  This file is part of the C166 Compiler package
;  Copyright KEIL ELEKTRONIK GmbH 1993 - 2003
;  Version 4.06
;------------------------------------------------------------------------------
;  START_V2.A66:  This code is executed after processor reset and provides the
;                 startup sequence for the C166v2/Super10 architecture CPU's.
;                 (i.e. XC161, XC164 ect.)
;
;  You may add this file to a uVision2 project - in this case it will be 
;  automatically assembled and linked.
;
;  For manual translation of this file use A166 with the following invocation:
;
;     A166 START_V2.A66 SET (<model>)
;
;     <model> determines the memory model and can be one of the following:
;         TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE or HLARGE
;
;  Example:  A166 START_V2.A66 SET (SMALL)
;
;  For manual linkage of the modified START_V2.OBJ file to your application
;  use the following L166 invocation:
;
;     L166 <your object file list>, START_V2.OBJ <controls>
;
;------------------------------------------------------------------------------
; Setup model-dependend Assembler controls
$CASE
$IF NOT TINY
$SEGMENTED
$ENDIF
; Settings for ADDRSEL calculation (do not change!)
KB          EQU    0x400     ; define KB constant for CS _SIZE calculation
MB          EQU    0x400*KB  ; define MB as 1024KB
;------------------------------------------------------------------------------
;
; Definitions for System and User Stack
; =====================================
;
; STKSZ: Maximum System Stack Size selection
;  Defines the system stack space that is used by CALL/RET and PUSH/POP 
;  instructions.  The system stack space must be adjusted according the actual
;  requirements of the application.
SSTSZ   EQU     0x200    ; set System Stack Size to 200H Bytes
;
; USTSZ: User Stack Size Definition 
;  Defines the user stack space available for automatics.  This stack space is
;  accessed by R0.  The user stack space must be adjusted according the actual
;  requirements of the application.
USTSZ   EQU     0x200    ; set User Stack Size to 200H Bytes.
;
; UST1SZ: User Stack Size for local register bank 1
;  Defines the user stack space available for the interrupt functions that are
;  assigned to the local register bank 1.  Since the compiler cannot copy the R0
;  value to local register banks, the user stack must be assign separately.
;  If you have no interrupt functions assigned to local register bank 1, you may
;  set UST1SZ to 0.
UST1SZ   EQU    0x20     ; set User Stack Size to 20H Bytes.
;
; UST2SZ: User Stack Size for local register bank 2
;  Defines the user stack space available for the interrupt functions that are
;  assigned to the local register bank 1.  Since the compiler cannot copy the R0
;  value to local register banks, the user stack must be assign separately.
;  If you have no interrupt functions assigned to local register bank 2, you may
;  set UST2SZ to 0.
UST2SZ   EQU    0x20     ; set User Stack Size to 20H Bytes.
;
;
; Definitions for Startup Code
; ============================
;
; CLR_MEMORY: Disable Memory Zero Initialization of RAM area
; --- Set CLR_MEMORY = 0 to disable memory zero initilization
$SET (CLR_MEMORY = 1)
;
; INIT_VARS: Disable Variable Initialization
; --- Set INIT_VARS = 0 to disable variable initilization
$SET (INIT_VARS = 1)
;
; DPPUSE:  Re-assign DPP registers
; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you
;                    are not using the L166 DPPUSE directive.
$SET (DPPUSE = 1)
;
; DPP3USE: Use DPP3 register during variable initilization
; --- Set DPP3USE = 0 to disable the usage of DPP3 during initilization of
;                     variables.  This option might be required if you write
;                     program parts that are reloaded during application 
;                     execution and increase code size of the startup code.
$SET (DPP3USE = 1)
;
;
; Definitions for CPU Configuration Register CPUCON1
; ==================================================
;
; ZCJ: Zero Cycle Jump Function (CPUCON1.0):
_ZCJ EQU 1 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Enable Zero Cycle Jump Function
;
; BP: Branch Prediction Unit (CPUCON1.1):
_BP EQU 1 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Enable Branch Prediction Unit
;
; INTSCXT: Interruptability of Switch Context Instruction (CPUCON1.2):
_INTSCXT EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Enable Interruption of SCXT instruction
;
; SGTDIS: Disable Segmentation Control (CPUCON1.3):
$IF TINY
_SGTDIS EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
$ELSE
_SGTDIS  EQU    0       ; enable segmented mode (Reset Value)
$ENDIF
;
; WDTCTL: Watchdog Timer Control (CPUCON1.4):
_WDTCTL EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = DISWDT/ENWDT always executable
;
; VECSC: Vector Table Scaling Factor (CPUCON1.5 .. CPUCON1.6)
_VECSC EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Space between two vectors is 4 words
                        ; 2 = Space between two vectors is 8 words
                        ; 3 = Space between two vectors is 16 words
;
;
; Definitions for CPU Configuration Register CPUCON2
; ==================================================
;
; INIT_CPUCON2: Init CPUCON2 register
; --- Set INIT_CPUCON2 = 1 to initilize the SYSCON1 register
$SET (INIT_CPUCON2 = 0) ; default: do not initilize CPUCON2  
;
; SL: Short Loop Mode (CPUCON2.0)
_SL EQU 1 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Short Loop mode enabled
;
; FASTPEC: Fast Pec Event Injection (CPUCON2.1)
_FASTPEC  EQU   1       ; 0 = Direct Injection of PEC Events disabled
                        ; 1 = Direct Injection of PEC Events enabled
;
; FASTBL: Fast Block Transfer Injection (CPUCON2.2)
_FASTBL   EQU   0       ; 0 = Direct Injection for Block Transfers disabled
                        ; 1 = Direct Injection for Block Transfers enabled
;
; RETST: Return Stack (CPUCON2.3)
_RETST EQU 1 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Return Stack enabled
;
; OVRUN: Pipeline Bubble Overrun (CPUCON2.4)
_OVRUN EQU 1 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Overrun of Pipeline Bubbles allowed
;
; ZSC: Zero Cycle Jump Cache (CPUCON2.5)
_ZSC      EQU   1       ; 0 = Zero Cycle Jump Cache disabled
                        ; 1 = Zero Cycle Jump Cache enabled
;
; STEN: Stall Instruction (CPUCON2.6)
_STEN EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Stall instruction enabled
;
; EIOIAEN: Early IO Injection Acknowledge
_EIOIAEN  EQU   1       ; 0 = Injection ack. by destructive read not guaranteed
;                       ; 1 = Injection ack. by destructive read guaranteed
; 
; BYPF: Fetch Bypass Control (CPUCON2.8)
_BYPF EQU 1 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Bypass Path from Fetch to Decode enabled
;
; BYPPF: Prefecth Bypass Control (CPUCON2.9)
_BYPPF EQU 1 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Bypass Path from Prefetch to Decode enabled
;
; FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
_FIFOFED EQU 3 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = FIFO filled with up to 1 instruction per cycle
                        ; 2 = FIFO filled with up to 2 instructions per cycle
                        ; 3 = FIFO filled with up to 3 instructions per cycle
;
; FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15)
_FIFODEPTH EQU 8 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = 1 FIFO entry
                        ; ...
                        ; 8 = 8 FIFO entries
                        ; 9 - 15 = reserved
;
;
; Definitions for System Configuration Register SYSCON1
; =====================================================
;
; INIT_SYSCON1: Init SYSCON1 register
; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON1 register
$SET (INIT_SYSCON1 = 0) ; Uv2/Dave /Dave/                                                                                                                              
;
; SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
_SLEEPCON EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = SLEEP mode entered upone IDLE instruction
                        ; 2 - 3 = reserved
;
; PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
_PDCFG EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Port drivers are off in IDLE or Sleep mode
                        ; 2 = Port drivers are off in Powerdown mode
                        ; 3 = reserved
;
; PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
_PFCFG EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = Program Flash is off in IDLE or Sleep mode
                        ; 2 - 3 = reserved
;
; CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
_CPSYS EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; 1 = clock signal for CPU is PLL frequency / 2
                        ; 2 - 7 = reserved
;
;
; Definitions for System Configuration Register SYSCON3
; =====================================================
;
; INIT_SYSCON3: Init SYSCON3 register
; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
$SET (INIT_SYSCON3 = 1) ; Uv2/Dave /Dave/                                                                                                                              
;
; SYSCON3:  Power Management (disable on-chip peripherals)
;
ADCDIS  EQU     0       ; 1 = disable Analog/Digital Converter    (SYSCON3.0)
ASC0DIS EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
SSC0DIS EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
GPTDIS EQU 0 ; Uv2/Dave /Dave/                                                                                                                              
                        ; reserved                                (SYSCON3.4)
FMDIS EQU 0 ; Uv2/Dave /Dave/                                                                                                                              

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