📄 mixer.va
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// -----------------------------------------------------------
//
// Additional material to the book
// Modeling and Simulation for RF System Design
//
// THIS MODEL IS LICENSED TO YOU "AS IT IS" AND WITH NO WARRANTIES,
// EXPRESSED OR IMPLIED. THE AUTHORS SPECIFICALLY DISCLAIM ALL IMPLIED
// WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// THEY MUST NOT HAVE ANY RESPONSIBILITY FOR ANY DAMAGES, FINANCIAL OR
// LEGAL CLAIMS WHATEVER.
// -----------------------------------------------------------
//
// Name: Verilog-A model of a mixer
//
// Source: mixer.va
// -----------------------------------------------------------
`include "constants.h"
`include "discipline.h"
module mixer (rf_in, lo_in, if_out, gnd);
inout rf_in, lo_in, if_out, gnd;
electrical rf_in, lo_in, if_out, gnd;
electrical p1, p2, p3, p4;
parameter real gain = 0; // Gain in dB
parameter real r_rf = 50; // Input resistance RF Input
parameter real r_lo = 50; // Input resistance LO Input
parameter real r_if = 50; // Output resistance IF Output
parameter real fg = 1G; // 3dB frequency
parameter real fnoise = 5; // Noise figure in dB
parameter real ip3 = -30; // IP3 in dBm
real gain_lin, ip3_lin, noise, a, b, inmax, outmax;
analog begin
@ (initial_step) begin
gain_lin = pow (10, gain/10);
ip3_lin = sqrt (pow (10, (ip3/10)) * 2*r_rf*0.001);
noise = 4*`P_K*(pow(10,fnoise/10)-1)*$temperature*r_rf;
a = sqrt((gain_lin*r_if)/r_rf);
b = (4*a)/(3*ip3_lin*ip3_lin);
inmax = sqrt(a/(3*b));
outmax = (2*a*inmax)/3;
end
// noise source
V(rf_in,p1) <+ white_noise (noise, "noise");
// input resistance
V(p1,gnd) <+ I(p1,gnd) * r_rf;
V(lo_in,gnd) <+ I(lo_in,gnd) * r_lo;
// Gilbert cell
V(p2,gnd) <+ V(p1,gnd) * V(lo_in,gnd);
// frequency response
V(p3,gnd) <+ laplace_nd(V(p2,gnd), {1}, {1, 1/`M_TWO_PI/fg});
// nonlinear characteristic
if (abs(V(p3,gnd)) < inmax)
V(p4,gnd) <+ 2 * (a - b*V(p3,gnd)*V(p3,gnd)) * V(p3,gnd);
else if (V(p2,gnd) > 0)
V(p4,gnd) <+ 2 * outmax;
else
V(p4,gnd) <+ -2 * outmax;
// output resistance
V(if_out,p4) <+ I(if_out,p4) * r_if;
end
endmodule
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