lna.va

springer_-modeling_and_simulation_for_rf_system_design所有配套光盘源码5-11章

// -----------------------------------------------------------
// 
// Additional material to the book
// Modeling and Simulation for RF System Design
//
// THIS MODEL IS LICENSED TO YOU "AS IT IS" AND WITH NO WARRANTIES, 
// EXPRESSED OR IMPLIED. THE AUTHORS SPECIFICALLY DISCLAIM ALL IMPLIED 
// WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
// THEY MUST NOT HAVE ANY RESPONSIBILITY FOR ANY DAMAGES, FINANCIAL OR
// LEGAL CLAIMS WHATEVER.
// -----------------------------------------------------------
//
// Name:      Verilog-A model of an LNA 
//
// Source:    lna.va
// -----------------------------------------------------------


`include "constants.h"
`include "discipline.h"

module amp (in, out, gnd);

  inout in, out, gnd;
  electrical in, out, gnd;
  electrical p1, p2, p3;

  parameter real gain = 6.8;       // Gain in dB
  parameter real rin = 50;         // Input resistance
  parameter real rout = 50;        // Output resistance
  parameter real fg = 10M;         // 3 dB frequency
  parameter real fnoise = 5;       // Noise figure in dB
  parameter real ip3 = 1.9;        // IP3 in dBm

  real gain_lin, ip3_lin, noise, a, b, inmax, outmax;

  analog begin
    @ (initial_step) begin
      gain_lin = pow (10, gain/10);
      ip3_lin = sqrt ((pow (10, ip3/10)) * 2*rin*0.001);
      noise = 4*`P_K*(pow(10,fnoise/10)-1)*$temperature*rin;
      a = sqrt((gain_lin*rout)/rin);
      b = (4*a)/(3*ip3_lin*ip3_lin);
      inmax = sqrt(a/(3*b));
      outmax = (2*a*inmax)/3;
    end

    // noise source
    V(in,p1) <+ white_noise (noise, "noise");

    // input resistance
    V(p1,gnd) <+ I(p1,gnd) * rin;

    // frequency response
    V(p2,gnd) <+ laplace_nd(V(p1,gnd), {1}, {1, 1/`M_TWO_PI/fg});

    // nonlinear characteristic
    if (abs(V(p2,gnd)) < inmax)
       V(p3,gnd) <+ 2 * (a - b*V(p2,gnd)*V(p2,gnd)) * V(p2,gnd);
    else if (V(p2,gnd) > 0)
       V(p3,gnd) <+ 2 * outmax;
    else
       V(p3,gnd) <+ -2 * outmax;

    // output resistance
    V(out,p3) <+ I(out,p3) * rout;

  end

endmodule