lna.vhd

springer_-modeling_and_simulation_for_rf_system_design所有配套光盘源码5-11章

-- -----------------------------------------------------------
-- 
-- Additional material to the book
-- Modeling and Simulation for RF System Design
-- 
--
-- THIS MODEL IS LICENSED TO YOU "AS IT IS" AND WITH NO WARRANTIES, 
-- EXPRESSED OR IMPLIED. THE AUTHORS SPECIFICALLY DISCLAIM ALL IMPLIED 
-- WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
-- THEY MUST NOT HAVE ANY RESPONSIBILITY FOR ANY DAMAGES, FINANCIAL OR
-- LEGAL CLAIMS WHATEVER.
-- -----------------------------------------------------------

-- Name:      Low-noise amplifier
-- 
-- Description:
-- This model describes an amplifier stage with first order
-- transfer function and output voltage compression. This block
-- is called low-noise amplifier when used in RF applications
-- although noise modeling is not yet included.
--
-- Literature:
-- 
-- Dependencies: 
-- -----------------------------------------------------------
-- Logical Library         Design unit
-- -----------------------------------------------------------
-- IEEE_proposed           ELECTRICAL_SYSTEMS
-- IEEE                    MATH_REAL
-- -----------------------------------------------------------
--
-- Source:
-- lna.vhd
-- -----------------------------------------------------------

library IEEE, IEEE_proposed;                                            
  use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
  use IEEE.MATH_REAL.all;

entity LNA IS 
  generic (GP_DB     : REAL := 0.0;       -- open-loop power gain [dB]
           IP3_DBM   : REAL := -20.0;     -- input referenced IP3  [dBm] 
           FNOISE_DB : REAL := 0.0;       -- noise figure [dB]
           RIN       : REAL := 50.0;	  -- input resistance [Ohm], MIN: >0.0
	   ROUT      : REAL := 50.0;	  -- output resistance [Ohm], MIN: >0.0
           FG        : REAL := REAL'HIGH  -- dominant pole [Hz], MIN: >0.0
           );
  port (terminal P_IN  : ELECTRICAL;    -- input terminal
        terminal P_OUT : ELECTRICAL;    -- output terminal 
        terminal VDD   : ELECTRICAL;    -- supply voltage 
        terminal GND   : ELECTRICAL     -- reference terminal
        );
begin
  assert RIN>0.0;
  assert ROUT>0.0;
  assert FG>0.0;
end entity LNA;

architecture RF of LNA is
  constant GP_LIN   : REAL:= 10**(GP_DB/10.0);          -- linear value of power gain
  constant IP3_LIN  : REAL:= 10**((IP3_DBM-30.0)/10.0); -- linear value of ip3
  constant A        : REAL:= SQRT(GP_LIN*ROUT/RIN);     -- linear value of voltage gain
  constant IP3      : REAL:= SQRT(IP3_LIN*2.0*RIN);     -- linear value of ip3 voltage
  constant B        : REAL:= A/(IP3*IP3)*4.0/3.0;       -- third order coefficent
  constant INMAX    : REAL:= SQRT(A/(3.0*B));           -- maximum input voltage for clipping
  constant OUTMAX   : REAL:= 2.0*A/3.0*INMAX;           -- output voltage at clipping
  constant TENV     : REAL:= 300.0;
  constant NOISE_LVL: REAL:= 4.0*1.38e-23*(10**(FNOISE_DB/10.0)-1.0)*TENV*RIN;   
  terminal U_IN     : ELECTRICAL;
  terminal U_IN_F   : ELECTRICAL;
  terminal U_OUT    : ELECTRICAL;
  quantity V_NOISE across I_NOISE through P_IN to U_IN;
  quantity V_RIN   across I_RIN   through U_IN to GND;
  quantity V_UINF  across I_UINF  through U_IN_F to GND;
  quantity V_LIM   across I_LIM   through U_OUT to GND;      
  quantity V_ROUT  across I_ROUT  through U_OUT to P_OUT;              

begin

  -- input stage: noise figure, input resistance
  V_NOISE == 0.0;
  V_RIN == RIN * I_RIN;
  
  -- transmission stage: gain, voltage limitation, transfer function
  V_UINF == V_RIN'LTF((0 => 1.0), (1.0, 1.0/MATH_2_PI/FG));

  if abs(V_UINF)<INMAX use
    V_LIM == 2.0*(A - B*V_UINF*V_UINF)*V_UINF;
  elsif V_UINF > 0.0 use
    V_LIM == 2.0*OUTMAX;
  else
    V_LIM == -2.0*OUTMAX;
  end use;

  -- output stage:  output resistance
  V_ROUT == ROUT * I_ROUT; 

end architecture RF;

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