divider_ent.vhd

来自「springer_-modeling_and_simulation_for_rf」· VHDL 代码 · 共 43 行

-- -----------------------------------------------------------
-- 
-- Additional material to the book
-- Modeling and Simulation for RF System Design
-- 
--
-- THIS MODEL IS LICENSED TO YOU "AS IT IS" AND WITH NO WARRANTIES, 
-- EXPRESSED OR IMPLIED. THE AUTHORS SPECIFICALLY DISCLAIM ALL IMPLIED 
-- WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
-- THEY MUST NOT HAVE ANY RESPONSIBILITY FOR ANY DAMAGES, FINANCIAL OR
-- LEGAL CLAIMS WHATEVER.
-- -----------------------------------------------------------

-- Name:      DIVIDER entity Declaration
-- 
-- Description:
-- The entity DIVIDER is declared. The architecture is described
-- in the file divider_simple.vhd. The entity is a primary design
-- unit. It has to be analyzed prior to the analysis of the 
-- architecture.
-- 
-- Literature:
-- 
-- Dependencies: 
-- -----------------------------------------------------------
-- Logical Library         Design unit
-- -----------------------------------------------------------
-- 
-- -----------------------------------------------------------
--
-- Source:
-- divider_ent.vhd
-- -----------------------------------------------------------


entity DIVIDER is
       generic (N    : POSITIVE    -- output pulse after N input pulses
               );
       port    (INP  : in   BIT;   -- input
                OUTP : out  BIT    -- output
               );
end entity DIVIDER;