bench.xml

springer_-modeling_and_simulation_for_rf_system_design所有配套光盘源码5-11章

<?xml version="1.0" encoding="ISO-8859-1"?>
<?xml-stylesheet href="/usr/local/vamdoc-1.0.2-kluwer/config/model.xsl" type="text/xsl"?>
<!DOCTYPE model SYSTEM "/usr/local/vamdoc-1.0.2-kluwer/config/model.dtd"><model>
  <symbol>../symbol/bench.png</symbol>
  <comments>
    <title>Simple Digital Divider</title>
    <model_name>BENCH(BENCH_SIMPLE)</model_name>
    <library>N/A</library>
    <structure>N/A</structure>
    <description>The BIT-value signal CLK changes its value after 1 ms. This<br></br>signal is divided by the model DIVIDER(SIMPLE) using N=5. <br></br>In an intervall of 10 ms there occur 5 pulses of CLK and one<br></br>pulse of the dividers output OUTP. The simulation should<br></br>run until 50 ms.<br></br><br></br></description>
    <link_source><A HREF="../src/bench.vhd">See source code</A></link_source>
    <dependency>
      <library>WORK</library>
      <design_unit>DIVIDER(SIMPLE)</design_unit>
    </dependency>
  </comments>
  <interface>
  </interface>
</model>