d2a.xml

springer_-modeling_and_simulation_for_rf_system_design所有配套光盘源码5-11章

<?xml version="1.0" encoding="ISO-8859-1"?>
<?xml-stylesheet href="/usr/local/vamdoc-1.0.2-kluwer/config/model.xsl" type="text/xsl"?>
<!DOCTYPE model SYSTEM "/usr/local/vamdoc-1.0.2-kluwer/config/model.dtd"><model>
  <symbol>../symbol/d2a.png</symbol>
  <comments>
    <title>D-to-A Converter</title>
    <model_name>D2A(IDEAL)</model_name>
    <library>N/A</library>
    <structure>N/A</structure>
    <description>The output voltage is set to VHIGH for input signal values<br></br>of '1' and 'H'. Otherwise it is set to 0.0. The function To_Bit<br></br>from the package STD_LOGIC_1164 is used for signal conversion.<br></br>The characteristic of the changes of the output voltage depends<br></br>on the values of the generic parameters.<br></br><br></br></description>
    <link_source><A HREF="../src/d2a.vhd">See source code</A></link_source>
    <dependency>
      <library>IEEE_proposed</library>
      <design_unit>ELECTRICAL_SYSTEMS</design_unit>
    </dependency>
    <dependency>
      <library>IEEE</library>
      <design_unit>STD_LOGIC_1164</design_unit>
    </dependency>
  </comments>
  <interface>
    <parameter>
      <name>VHIGH</name>
      <type>REAL</type>
      <default>5.0</default>
      <unit>V</unit>
      <comment> high voltage </comment>
    </parameter>
    <parameter>
      <name>TD_01</name>
      <type>TIME</type>
      <default>0ns</default>
      <unit>TIME</unit>
      <comment> posedge delay </comment>
    </parameter>
    <parameter>
      <name>TD_10</name>
      <type>TIME</type>
      <default>0ns</default>
      <unit>TIME</unit>
      <comment> negedge delay </comment>
    </parameter>
    <parameter>
      <name>TRISE</name>
      <type>REAL</type>
      <default>0.0</default>
      <unit>s</unit>
      <comment> rising time </comment>
    </parameter>
    <parameter>
      <name>TFALL</name>
      <type>REAL</type>
      <default>0.0</default>
      <unit>s</unit>
      <comment> falling time </comment>
    </parameter>
    <port>
      <port_id>signal</port_id>
      <name>S_IN</name>
      <port_type>STD_LOGIC</port_type>
      <mode>in</mode>
      <comment> input signal</comment>
    </port>
    <port>
      <port_id>terminal</port_id>
      <name>OUTP</name>
      <port_type>ELECTRICAL</port_type>
      <comment> output terminal</comment>
    </port>
  </interface>
</model>