ramvar.ini

w588d开发例程

;  0WITH_VSA_VC8
;  0WITH_VSB_VC8
;  0WITH_VSC_VC8
;  0WITH_VSD_VC8
;  0WITH_VSE_VC8
;  0WITH_VSF_VC8
;  0WITH_VS0A_VC4
;  0WITH_VS0B_VC4
;  0WITH_VS0C_VC4
;  0WITH_VS0D_VC4
;  0WITH_VS1A_VC4
;  0WITH_VS1B_VC4
;  0WITH_VS2A_VC4
;  0WITH_VS2B_VC4
;  0WITH_VS3_VC4
;  0WITH_VS4_VC4
;  0WITH_VS5_VC4
;  0WITH_VS6_VC4
;  0WITH_VS7_VC4
;  0WITH_VS8_VC4
;  0WITH_VS9_VC4
;  0WITH_VSA_VC4
;  0WITH_VSB_VC4
;  0WITH_VSC_VC4
;  0WITH_VSD_VC4
;  0WITH_VSE_VC4
;  0WITH_VSF_VC4
;  0WITH_VS0A_VMDPC8
;  0WITH_VS0B_VMDPC8
;  0WITH_VS0C_VMDPC8
;  0WITH_VS0D_VMDPC8
;  0WITH_VS1A_VMDPC8
;  0WITH_VS1B_VMDPC8
;  0WITH_VS2A_VMDPC8
;  0WITH_VS2B_VMDPC8
;  0WITH_VS3_VMDPC8
;  0WITH_VS4_VMDPC8
;  0WITH_VS5_VMDPC8
;  0WITH_VS6_VMDPC8
;  0WITH_VS7_VMDPC8
;  0WITH_VS8_VMDPC8
;  0WITH_VS9_VMDPC8
;  0WITH_VSA_VMDPC8
;  0WITH_VSB_VMDPC8
;  0WITH_VSC_VMDPC8
;  0WITH_VSD_VMDPC8
;  0WITH_VSE_VMDPC8
;  0WITH_VSF_VMDPC8
;  0WITH_VS0A_PCSPC8
;  0WITH_VS0B_PCSPC8
;  0WITH_VS0C_PCSPC8
;  0WITH_VS0D_PCSPC8
;  0WITH_VS1A_PCSPC8
;  0WITH_VS1B_PCSPC8
;  0WITH_VS2A_PCSPC8
;  0WITH_VS2B_PCSPC8
;  0WITH_VS3_PCSPC8
;  0WITH_VS4_PCSPC8
;  0WITH_VS5_PCSPC8
;  0WITH_VS6_PCSPC8
;  0WITH_VS7_PCSPC8
;  0WITH_VS8_PCSPC8
;  0WITH_VS9_PCSPC8
;  0WITH_VSA_PCSPC8
;  0WITH_VSB_PCSPC8
;  0WITH_VSC_PCSPC8
;  0WITH_VSD_PCSPC8
;  0WITH_VSE_PCSPC8
;  0WITH_VSF_PCSPC8
;  0WITH_VS0A_VMDLP8
;  0WITH_VS0B_VMDLP8
;  0WITH_VS0C_VMDLP8
;  0WITH_VS0D_VMDLP8
;  0WITH_VS1A_VMDLP8
;  0WITH_VS1B_VMDLP8
;  0WITH_VS2A_VMDLP8
;  0WITH_VS2B_VMDLP8
;  0WITH_VS3_VMDLP8
;  0WITH_VS4_VMDLP8
;  0WITH_VS5_VMDLP8
;  0WITH_VS6_VMDLP8
;  0WITH_VS7_VMDLP8
;  0WITH_VS8_VMDLP8
;  0WITH_VS9_VMDLP8
;  0WITH_VSA_VMDLP8
;  0WITH_VSB_VMDLP8
;  0WITH_VSC_VMDLP8
;  0WITH_VSD_VMDLP8
;  0WITH_VSE_VMDLP8
;  0WITH_VSF_VMDLP8
;  0WITH_VS0A_PCSLP8
;  0WITH_VS0B_PCSLP8
;  0WITH_VS0C_PCSLP8
;  0WITH_VS0D_PCSLP8
;  0WITH_VS1A_PCSLP8
;  0WITH_VS1B_PCSLP8
;  0WITH_VS2A_PCSLP8
;  0WITH_VS2B_PCSLP8
;  0WITH_VS3_PCSLP8
;  0WITH_VS4_PCSLP8
;  0WITH_VS5_PCSLP8
;  0WITH_VS6_PCSLP8
;  0WITH_VS7_PCSLP8
;  0WITH_VS8_PCSLP8
;  0WITH_VS9_PCSLP8
;  0WITH_VSA_PCSLP8
;  0WITH_VSB_PCSLP8
;  0WITH_VSC_PCSLP8
;  0WITH_VSD_PCSLP8
;  0WITH_VSE_PCSLP8
;  0WITH_VSF_PCSLP8
;  0WITH_VS0A_PC8VMDPCS
;  0WITH_VS0B_PC8VMDPCS
;  0WITH_VS0C_PC8VMDPCS
;  0WITH_VS0D_PC8VMDPCS
;  0WITH_VS1A_PC8VMDPCS
;  0WITH_VS1B_PC8VMDPCS
;  0WITH_VS2A_PC8VMDPCS
;  0WITH_VS2B_PC8VMDPCS
;  0WITH_VS3_PC8VMDPCS
;  0WITH_VS4_PC8VMDPCS
;  0WITH_VS5_PC8VMDPCS
;  0WITH_VS6_PC8VMDPCS
;  0WITH_VS7_PC8VMDPCS
;  0WITH_VS8_PC8VMDPCS
;  0WITH_VS9_PC8VMDPCS
;  0WITH_VSA_PC8VMDPCS
;  0WITH_VSB_PC8VMDPCS
;  0WITH_VSC_PC8VMDPCS
;  0WITH_VSD_PC8VMDPCS
;  0WITH_VSE_PC8VMDPCS
;  0WITH_VSF_PC8VMDPCS
;  0WITH_VS0A_LP8VMDPCS
;  0WITH_VS0B_LP8VMDPCS
;  0WITH_VS0C_LP8VMDPCS
;  0WITH_VS0D_LP8VMDPCS
;  0WITH_VS1A_LP8VMDPCS
;  0WITH_VS1B_LP8VMDPCS
;  0WITH_VS2A_LP8VMDPCS
;  0WITH_VS2B_LP8VMDPCS
;  0WITH_VS3_LP8VMDPCS
;  0WITH_VS4_LP8VMDPCS
;  0WITH_VS5_LP8VMDPCS
;  0WITH_VS6_LP8VMDPCS
;  0WITH_VS7_LP8VMDPCS
;  0WITH_VS8_LP8VMDPCS
;  0WITH_VS9_LP8VMDPCS
;  0WITH_VSA_LP8VMDPCS
;  0WITH_VSB_LP8VMDPCS
;  0WITH_VSC_LP8VMDPCS
;  0WITH_VSD_LP8VMDPCS
;  0WITH_VSE_LP8VMDPCS
;  0WITH_VSF_LP8VMDPCS
;  0WITH_VS0A_TONE
;  0WITH_VS0B_TONE
;  0WITH_VS0C_TONE
;  0WITH_VS0D_TONE
;  0WITH_VS1A_TONE
;  0WITH_VS1B_TONE
;  0WITH_VS2A_TONE
;  0WITH_VS2B_TONE
;  0WITH_VS3_TONE
;  0WITH_VS4_TONE
;  0WITH_VS5_TONE
;  0WITH_VS6_TONE
;  0WITH_VS7_TONE
;  0WITH_VS8_TONE
;  0WITH_VS9_TONE
;  0WITH_VSA_TONE
;  0WITH_VSB_TONE
;  0WITH_VSC_TONE
;  0WITH_VSD_TONE
;  0WITH_VSE_TONE
;  0WITH_VSF_TONE
;  0WITH_VS0A_HQPC8
;  0WITH_VS0B_HQPC8
;  0WITH_VS0C_HQPC8
;  0WITH_VS0D_HQPC8
;  0WITH_VS1A_HQPC8
;  0WITH_VS1B_HQPC8
;  0WITH_VS2A_HQPC8
;  0WITH_VS2B_HQPC8
;  0WITH_VS3_HQPC8
;  0WITH_VS4_HQPC8
;  0WITH_VS5_HQPC8
;  0WITH_VS6_HQPC8
;  0WITH_VS7_HQPC8
;  0WITH_VS8_HQPC8
;  0WITH_VS9_HQPC8
;  0WITH_VSA_HQPC8
;  0WITH_VSB_HQPC8
;  0WITH_VSC_HQPC8
;  0WITH_VSD_HQPC8
;  0WITH_VSE_HQPC8
;  0WITH_VSF_HQPC8
;  0WITH_VS0A_HQ567
;  0WITH_VS0B_HQ567
;  0WITH_VS0C_HQ567
;  0WITH_VS0D_HQ567
;  0WITH_VS1A_HQ567
;  0WITH_VS1B_HQ567
;  0WITH_VS2A_HQ567
;  0WITH_VS2B_HQ567
;  0WITH_VS3_HQ567
;  0WITH_VS4_HQ567
;  0WITH_VS5_HQ567
;  0WITH_VS6_HQ567
;  0WITH_VS7_HQ567
;  0WITH_VS8_HQ567
;  0WITH_VS9_HQ567
;  0WITH_VSA_HQ567
;  0WITH_VSB_HQ567
;  0WITH_VSC_HQ567
;  0WITH_VSD_HQ567
;  0WITH_VSE_HQ567
;  0WITH_VSF_HQ567
;  0WITH_VS0A_VMD567
;  0WITH_VS0B_VMD567
;  0WITH_VS0C_VMD567
;  0WITH_VS0D_VMD567
;  0WITH_VS1A_VMD567
;  0WITH_VS1B_VMD567
;  0WITH_VS2A_VMD567
;  0WITH_VS2B_VMD567
;  0WITH_VS3_VMD567
;  0WITH_VS4_VMD567
;  0WITH_VS5_VMD567
;  0WITH_VS6_VMD567
;  0WITH_VS7_VMD567
;  0WITH_VS8_VMD567
;  0WITH_VS9_VMD567
;  0WITH_VSA_VMD567
;  0WITH_VSB_VMD567
;  0WITH_VSC_VMD567
;  0WITH_VSD_VMD567
;  0WITH_VSE_VMD567
;  0WITH_VSF_VMD567
;  0WITH_VS0A_HQ567_HW
;  0WITH_VS0B_HQ567_HW
;  0WITH_VS0C_HQ567_HW
;  0WITH_VS0D_HQ567_HW
;  0WITH_VS1A_HQ567_HW
;  0WITH_VS1B_HQ567_HW
;  0WITH_VS2A_HQ567_HW
;  0WITH_VS2B_HQ567_HW
;  0WITH_VS3_HQ567_HW
;  0WITH_VS4_HQ567_HW
;  0WITH_VS5_HQ567_HW
;  0WITH_VS6_HQ567_HW
;  0WITH_VS7_HQ567_HW
;  0WITH_VS8_HQ567_HW
;  0WITH_VS9_HQ567_HW
;  0WITH_VSA_HQ567_HW
;  0WITH_VSB_HQ567_HW
;  0WITH_VSC_HQ567_HW
;  0WITH_VSD_HQ567_HW
;  0WITH_VSE_HQ567_HW
;  0WITH_VSF_HQ567_HW
;  0WITH_VS0A_HQ569_HW
;  0WITH_VS0B_HQ569_HW
;  0WITH_VS0C_HQ569_HW
;  0WITH_VS0D_HQ569_HW
;  0WITH_VS1A_HQ569_HW
;  0WITH_VS1B_HQ569_HW
;  0WITH_VS2A_HQ569_HW
;  0WITH_VS2B_HQ569_HW
;  0WITH_VS3_HQ569_HW
;  0WITH_VS4_HQ569_HW
;  0WITH_VS5_HQ569_HW
;  0WITH_VS6_HQ569_HW
;  0WITH_VS7_HQ569_HW
;  0WITH_VS8_HQ569_HW
;  0WITH_VS9_HQ569_HW
;  0WITH_VSA_HQ569_HW
;  0WITH_VSB_HQ569_HW
;  0WITH_VSC_HQ569_HW
;  0WITH_VSD_HQ569_HW
;  0WITH_VSE_HQ569_HW
;  0WITH_VSF_HQ569_HW
;  0WITH_CH0_EVO
;  0WITH_CH1_EVO
;  0WITH_CH2_EVO

;Support WITH_SP channel variables ========================
CH_STATUS_SP                             EQU  0H ;  1,  0
CH_ISR_SYNTH_START_SP                    EQU  1H ;  2,  1
CH_DATA_ADDR_SP                          EQU  3H ;  2,  3
CH_RAMP_BUF1_SP                          EQU  3H ;  2,  3
CH_DATA_BANK_SP                          EQU  5H ;  1,  5
CH_PHRASE_REPEAT_NUM_SP                  EQU  6H ;  1,  6
CH_SENTENCE_START_ADDR_SP                EQU  7H ;  2,  7
CH_RAMP_BUF2_SP                          EQU  7H ;  2,  7
CH_SENTENCE_START_BANK_SP                EQU  9H ;  1,  9
; Size = 10  ==============================================

;Not support WITH_APM channel variables ========================

;Not support WITH_EAM channel variables ========================

;Not support WITH_E2A channel variables ========================

;Not support WITH_VC4 channel variables ========================

;Not support WITH_YAD channel variables ========================

;Support WITH_SIL channel variables ========================
CH_STATUS_SIL                            EQU  0H ;  1,  0
CH_ISR_SYNTH_START_SIL                   EQU  1H ;  2,  1
CH_DATA_ADDR_SIL                         EQU  3H ;  2,  3
CH_DATA_BANK_SIL                         EQU  5H ;  1,  5
CH_PHRASE_REPEAT_NUM_SIL                 EQU  6H ;  1,  6
CH_SENTENCE_START_ADDR_SIL               EQU  7H ;  2,  7
CH_SENTENCE_START_BANK_SIL               EQU  9H ;  1,  9
CH_OLD_SAMPLE_SIL                        EQU  AH ;  2, 10
CH_COUNTER_SIL                           EQU  CH ;  1, 12
CH_COUNTER2_SIL                          EQU  DH ;  1, 13
; Size = 14  ==============================================

;Support WITH_MDM channel variables ========================
CH_STATUS_MDM                            EQU  0H ;  1,  0
CH_ISR_SYNTH_START_MDM                   EQU  1H ;  2,  1
CH_DATA_ADDR_MDM                         EQU  3H ;  2,  3
CH_DATA_BANK_MDM                         EQU  5H ;  1,  5
CH_PHRASE_REPEAT_NUM_MDM                 EQU  6H ;  1,  6
CH_SENTENCE_START_ADDR_MDM               EQU  7H ;  2,  7
CH_SENTENCE_START_BANK_MDM               EQU  9H ;  1,  9
CH_OLD_SAMPLE_MDM                        EQU  AH ;  2, 10
CH_COUNTER_MDM                           EQU  CH ;  1, 12
CH_GAIN_BUFFER_MDM                       EQU  DH ;  2, 13
CH_SIGN_BUFFER_MDM                       EQU  FH ;  1, 15
CH_MDM_TMPREG_MDM                        EQU  FH ;  1, 15
CH_MDPCM_4TH_MDM                         EQU  FH ;  1, 15
CH_MDPCM_BUFFER_MDM                      EQU 10H ;  1, 16
; Size = 17  ==============================================

;Not support WITH_EMM channel variables ========================

;Not support WITH_MD6 channel variables ========================

;Not support WITH_PC8 channel variables ========================

;Not support WITH_LP8 channel variables ========================

;Not support WITH_P10 channel variables ========================

;Not support WITH_P16 channel variables ========================

;Not support WITH_VC8 channel variables ========================
CH_STATUS_MS                             EQU  0H ;  0,   0


;Support WITH_EVO channel variables ========================
CH_STATUS_EVO                            EQU  0H ;  1,   0

;     RAM addresses =======================================
RINIT_REG                                EQU  0H ;  1,   0
COMMON_FLAG                              EQU  1H ;  1,   1
COMMON_FLAG2                             EQU  2H ;  1,   2
PWM_MODE_VALUE                           EQU  3H ;  1,   3
SPEN_TMP                                 EQU  4H ;  0,   4
SUB_INDEX                                EQU  4H ;  0,   4
COMMAND_OPERAND                          EQU  4H ;  1,   4
RAMP_CHANNEL                             EQU  4H ;  1,   4
RAMP_OPERAND                             EQU  4H ;  1,   4
TEMP_REG1                                EQU  5H ;  2,   5
TEMP_REG2                                EQU  7H ;  2,   7
VS0A_START                               EQU  9H ;  0,   9
VS0B_START                               EQU  9H ;  0,   9
VS0C_START                               EQU  9H ;  0,   9
VS0D_START                               EQU  9H ;  0,   9
VS1A_START                               EQU  9H ; 17,   9
VS1B_START                               EQU 1AH ;  0,  26
VS2A_START                               EQU 1AH ;  0,  26
VS2B_START                               EQU 1AH ;  0,  26
MS_START                                 EQU 1AH ;  0,  26
EVO0_START                               EQU 1AH ;  0,  26
EVO1_START                               EQU 1AH ;  0,  26
USER_START                               EQU 1AH ; 26