📄 lcd.rpt
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_X009 = EXP(!CLEAN & !CNT10 & !CNT12 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
_X010 = EXP(!CLEAN & !CNT11 & !CNT12 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
_EQ015 = !BUSY & _X004 & _X005 & _X006 & _X007 & _X008 & _X009 &
_X010;
_X004 = EXP(!CLEAN & CNT20 & !CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
_X005 = EXP(!CLEAN & CNT20 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
_X006 = EXP(!CLEAN & !CNT20 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
_X007 = EXP(!CLEAN & !CNT10 & !CNT13 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
_X008 = EXP(!CLEAN & !CNT10 & !CNT11 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
_X009 = EXP(!CLEAN & !CNT10 & !CNT12 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
_X010 = EXP(!CLEAN & !CNT11 & !CNT12 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
-- Node name is 'DOUT6' = ':12'
-- Equation name is 'DOUT6', type is output
DOUT6 = DFFE( _EQ016 $ _EQ017, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = !BUSY & !CLEAN & CNT11 & CNT12 & CNT13 & CNT20 & !DOWN &
!_LC006 & !LEFT & !RIGHT & !UP & _X004 & _X005 & _X006
# !BUSY & !CLEAN & CNT10 & CNT12 & CNT13 & CNT20 & !DOWN &
!_LC006 & !LEFT & !RIGHT & !UP & _X004 & _X005 & _X006
# !BUSY & !CLEAN & CNT11 & CNT12 & !CNT13 & CNT22 & !DOWN &
!_LC006 & !LEFT & !RIGHT & !UP & _X004 & _X005 & _X006
# !BUSY & !CLEAN & CNT10 & CNT11 & !CNT13 & CNT20 & !DOWN &
!_LC006 & !LEFT & !RIGHT & !UP & _X004 & _X005 & _X006;
_X004 = EXP(!CLEAN & CNT20 & !CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
_X005 = EXP(!CLEAN & CNT20 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
_X006 = EXP(!CLEAN & !CNT20 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
_EQ017 = !BUSY & !_LC006 & _X004 & _X005 & _X006;
_X004 = EXP(!CLEAN & CNT20 & !CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
_X005 = EXP(!CLEAN & CNT20 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
_X006 = EXP(!CLEAN & !CNT20 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
-- Node name is 'DOUT7' = ':10'
-- Equation name is 'DOUT7', type is output
DOUT7 = DFFE( _EQ018 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ018 = !BUSY & !CNT10 & !CNT11 & !CNT12 & CNT13 & !CNT20 & !CNT21
# !BUSY & CNT10 & !CNT11 & !CNT12 & !CNT13 & !CNT20 & !CNT21
# !BUSY & !CNT20 & !CNT21 & !CNT22
# !BUSY & _X011;
_X011 = EXP(!CLEAN & !DOWN & !LEFT & !RIGHT & !UP);
-- Node name is 'REQ' = ':8'
-- Equation name is 'REQ', type is output
REQ = DFFE(!BUSY $ GND, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|LPM_ADD_SUB:824|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( CNT22 $ _EQ019);
_EQ019 = CNT20 & CNT21;
-- Node name is '~644~1'
-- Equation name is '~644~1', location is LC006, type is buried.
-- synthesized logic cell
_LC006 = LCELL( _EQ020 $ GND);
_EQ020 = !CLEAN & !CNT10 & CNT12 & !CNT13 & CNT22 & !DOWN & !LEFT &
!RIGHT & !UP
# !CLEAN & !CNT10 & !CNT12 & CNT13 & CNT20 & !DOWN & !LEFT &
!RIGHT & !UP
# !CLEAN & CNT10 & CNT13 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & CNT10 & !CNT12 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & !CNT12 & CNT13 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP;
-- Node name is '~656~1'
-- Equation name is '~656~1', location is LC003, type is buried.
-- synthesized logic cell
_LC003 = LCELL( _EQ021 $ GND);
_EQ021 = !CLEAN & CNT10 & CNT12 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & CNT12 & !CNT13 & CNT20 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & !CNT12 & !CNT20 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & !CNT10 & !CNT20 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & !CNT13 & !CNT20 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP;
-- Node name is '~656~2'
-- Equation name is '~656~2', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ022 $ GND);
_EQ022 = !CLEAN & !CNT11 & !CNT20 & CNT21 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & !CNT11 & !CNT13 & CNT20 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & CNT10 & CNT20 & !DOWN & !LEFT & !RIGHT & !UP
# !CLEAN & CNT21 & CNT22 & !DOWN & !LEFT & !RIGHT & !UP;
-- Node name is '~668~1'
-- Equation name is '~668~1', location is LC002, type is buried.
-- synthesized logic cell
_LC002 = LCELL( _EQ023 $ GND);
_EQ023 = !CLEAN & !CNT10 & CNT12 & CNT21 & !DOWN & !LEFT & !UP
# !CLEAN & CNT10 & !CNT11 & !CNT12 & !DOWN & !LEFT & !UP
# !CLEAN & !CNT12 & CNT20 & !CNT21 & !DOWN & !LEFT & !UP
# !CLEAN & !CNT10 & !CNT20 & !CNT22 & !DOWN & !LEFT & !UP
# !CLEAN & !CNT10 & !CNT13 & !CNT20 & !DOWN & !LEFT & !UP;
-- Node name is '~668~2'
-- Equation name is '~668~2', location is LC001, type is buried.
-- synthesized logic cell
_LC001 = LCELL( _EQ024 $ GND);
_EQ024 = !CLEAN & !CNT12 & !CNT20 & !CNT22 & !DOWN & !LEFT & !UP
# !CLEAN & !CNT11 & !CNT12 & !CNT22 & !DOWN & !LEFT & !UP
# !CLEAN & !CNT11 & !CNT20 & !CNT22 & !DOWN & !LEFT & !UP
# !CLEAN & CNT21 & CNT22 & !DOWN & !LEFT & !UP
# !CLEAN & CNT20 & CNT22 & !DOWN & !LEFT & !UP;
-- Node name is '~674~1'
-- Equation name is '~674~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ025 $ GND);
_EQ025 = !BUSY & !CLEAN & CNT10 & CNT11 & CNT12 & !CNT20 & CNT21 &
!CNT22 & !DOWN & !RIGHT & !UP
# !BUSY & !CLEAN & !CNT10 & CNT11 & CNT12 & !CNT13 & CNT20 &
!CNT22 & !DOWN & !RIGHT & !UP
# !BUSY & !CLEAN & !CNT10 & !CNT11 & CNT13 & CNT20 & CNT21 &
!CNT22 & !DOWN & !RIGHT & !UP
# !BUSY & !CLEAN & CNT10 & CNT11 & !CNT12 & !CNT20 & !CNT21 &
CNT22 & !DOWN & !RIGHT & !UP
# !BUSY & !CLEAN & !CNT10 & !CNT11 & CNT12 & !CNT20 & !CNT21 &
CNT22 & !DOWN & !RIGHT & !UP;
-- Node name is '~674~2'
-- Equation name is '~674~2', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ026 $ GND);
_EQ026 = !BUSY & !CLEAN & !CNT11 & CNT12 & !CNT13 & !CNT20 & !CNT21 &
CNT22 & !DOWN & !RIGHT & !UP
# !BUSY & !CLEAN & !CNT11 & CNT12 & CNT20 & CNT21 & !CNT22 &
!DOWN & !RIGHT & !UP
# !BUSY & !CLEAN & !CNT10 & !CNT13 & !CNT20 & !CNT21 & CNT22 &
!DOWN & !RIGHT & !UP
# !BUSY & !CLEAN & CNT11 & CNT20 & !CNT21 & !CNT22 & !DOWN &
!RIGHT & !UP
# !BUSY & !DOWN & LEFT & !UP;
-- Node name is '~680~1'
-- Equation name is '~680~1', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ027 $ GND);
_EQ027 = !BUSY & !CLEAN & CNT10 & CNT11 & !CNT12 & !CNT13 & !CNT20 &
!CNT21 & CNT22 & !DOWN & !RIGHT
# !BUSY & !CLEAN & CNT11 & !CNT12 & !CNT13 & CNT20 & CNT21 &
!CNT22 & !DOWN & !RIGHT
# !BUSY & !CLEAN & CNT10 & !CNT11 & CNT13 & !CNT20 & !CNT21 &
CNT22 & !DOWN & !RIGHT
# !BUSY & !CLEAN & !CNT11 & CNT12 & CNT13 & !CNT20 & !CNT21 &
CNT22 & !DOWN & !RIGHT
# !BUSY & !CLEAN & !CNT10 & !CNT11 & !CNT13 & !CNT20 & !CNT21 &
CNT22 & !DOWN & !RIGHT;
-- Node name is '~680~2'
-- Equation name is '~680~2', location is LC014, type is buried.
-- synthesized logic cell
_LC014 = LCELL( _EQ028 $ GND);
_EQ028 = !BUSY & !CLEAN & CNT11 & CNT12 & CNT13 & CNT21 & !CNT22 &
!DOWN & !RIGHT
# !BUSY & !CLEAN & CNT10 & CNT11 & CNT12 & !CNT20 & !CNT22 &
!DOWN & !RIGHT
# !BUSY & !CLEAN & !CNT10 & CNT12 & CNT20 & CNT21 & !CNT22 &
!DOWN & !RIGHT
# !BUSY & !CLEAN & CNT10 & !CNT11 & CNT20 & !CNT21 & !CNT22 &
!DOWN & !RIGHT
# !BUSY & !CLEAN & CNT10 & !CNT12 & !CNT13 & CNT20 & !CNT22 &
!DOWN & !RIGHT;
-- Node name is '~680~3'
-- Equation name is '~680~3', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ029 $ GND);
_EQ029 = !BUSY & !CLEAN & CNT10 & !CNT12 & CNT20 & !CNT21 & !CNT22 &
!DOWN & !RIGHT
# !BUSY & !CLEAN & !CNT10 & CNT13 & CNT21 & !CNT22 & !DOWN &
!RIGHT
# !BUSY & !CLEAN & CNT13 & !CNT20 & CNT21 & !CNT22 & !DOWN &
!RIGHT
# !BUSY & !DOWN & UP
# !BUSY & !DOWN & LEFT;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X004 occurs in LABs A, B
Project Information e:\作业\eda\yejing\lcd.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,108K
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