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📄 lcd.rpt

📁 用chdl编写液晶块驱动程序。有详细的说明
💻 RPT
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s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                        e:\作业\eda\yejing\lcd.rpt
lcd

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (32)    25    B       SOFT      t        0      0   0    0    3    0    1  |LPM_ADD_SUB:824|addcore:adder|addcore:adder0|result_node2
  (8)     5    A       DFFE   +  t        0      0   0    0    4    6   17  CNT22 (:34)
  (7)     4    A       TFFE   +  t        0      0   0    0    1    6   16  CNT21 (:35)
 (37)    21    B       TFFE   +  t        0      0   0    0    3    6   18  CNT20 (:36)
 (38)    20    B       TFFE   +  t        0      0   0    0    6    6    9  CNT13 (:37)
 (39)    19    B       TFFE   +  t        0      0   0    0    5    6   10  CNT12 (:38)
 (41)    17    B       TFFE   +  t        0      0   0    0    4    6    9  CNT11 (:39)
 (40)    18    B       TFFE   +  t        0      0   0    0    3    6   12  CNT10 (:40)
  (9)     6    A       SOFT    s t        1      0   1    5    5    1    0  ~644~1
  (6)     3    A       SOFT    s t        1      0   1    5    6    1    0  ~656~1
 (24)    32    B       SOFT    s t        0      0   0    5    6    1    0  ~656~2
  (5)     2    A       SOFT    s t        1      0   1    4    7    1    0  ~668~1
  (4)     1    A       SOFT    s t        1      0   1    4    5    1    0  ~668~2
 (27)    29    B       SOFT    s t        1      0   1    5    7    1    0  ~674~1
 (25)    31    B       SOFT    s t        1      0   1    6    7    1    0  ~674~2
 (17)    12    A       SOFT    s t        1      0   1    4    7    1    0  ~680~1
 (19)    14    A       SOFT    s t        1      0   1    4    7    1    0  ~680~2
 (26)    30    B       SOFT    s t        1      0   1    6    6    1    0  ~680~3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                        e:\作业\eda\yejing\lcd.rpt
lcd

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                               Logic cells placed in LAB 'A'
        +--------------------- LC10 DOUT0
        | +------------------- LC8 DOUT1
        | | +----------------- LC7 DOUT4
        | | | +--------------- LC5 CNT22
        | | | | +------------- LC4 CNT21
        | | | | | +----------- LC6 ~644~1
        | | | | | | +--------- LC3 ~656~1
        | | | | | | | +------- LC2 ~668~1
        | | | | | | | | +----- LC1 ~668~2
        | | | | | | | | | +--- LC12 ~680~1
        | | | | | | | | | | +- LC14 ~680~2
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':
LC5  -> - - * * - * * * * * * | * * | <-- CNT22
LC4  -> - - * * * - * * * * * | * * | <-- CNT21
LC3  -> - - * - - - - - - - - | * - | <-- ~656~1
LC12 -> * - - - - - - - - - - | * - | <-- ~680~1
LC14 -> * - - - - - - - - - - | * - | <-- ~680~2

Pin
43   -> - * * - - - - - - * * | * * | <-- BUSY
6    -> - - * - - * * * * * * | * * | <-- CLEAN
2    -> - - - - - - - - - - - | - - | <-- CLK
4    -> - * * - - * * * * * * | * * | <-- DOWN
5    -> - - * - - * * * * - - | * * | <-- LEFT
8    -> - - * - - * * - - * * | * * | <-- RIGHT
9    -> - - * - - * * * * - - | * * | <-- UP
LC25 -> - - - * - - - - - - - | * - | <-- |LPM_ADD_SUB:824|addcore:adder|addcore:adder0|result_node2
LC21 -> - - * * * * * * * * * | * * | <-- CNT20
LC20 -> - - * - - * * * - * * | * * | <-- CNT13
LC19 -> - - * - - * * * * * * | * * | <-- CNT12
LC17 -> - - * - - - - * * * * | * * | <-- CNT11
LC18 -> - - * - - * * * - * * | * * | <-- CNT10
LC32 -> - - * - - - - - - - - | * - | <-- ~656~2
LC29 -> - * - - - - - - - - - | * - | <-- ~674~1
LC31 -> - * - - - - - - - - - | * - | <-- ~674~2
LC30 -> * - - - - - - - - - - | * - | <-- ~680~3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        e:\作业\eda\yejing\lcd.rpt
lcd

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC26 DOUT2
        | +----------------------------- LC24 DOUT3
        | | +--------------------------- LC23 DOUT5
        | | | +------------------------- LC22 DOUT6
        | | | | +----------------------- LC28 DOUT7
        | | | | | +--------------------- LC25 |LPM_ADD_SUB:824|addcore:adder|addcore:adder0|result_node2
        | | | | | | +------------------- LC27 REQ
        | | | | | | | +----------------- LC21 CNT20
        | | | | | | | | +--------------- LC20 CNT13
        | | | | | | | | | +------------- LC19 CNT12
        | | | | | | | | | | +----------- LC17 CNT11
        | | | | | | | | | | | +--------- LC18 CNT10
        | | | | | | | | | | | | +------- LC32 ~656~2
        | | | | | | | | | | | | | +----- LC29 ~674~1
        | | | | | | | | | | | | | | +--- LC31 ~674~2
        | | | | | | | | | | | | | | | +- LC30 ~680~3
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> * * * * * * - * * * * * * * * * | * * | <-- CNT20
LC20 -> * * * * * - - - * - - - * * * * | * * | <-- CNT13
LC19 -> * * * * * - - - * * - - - * * * | * * | <-- CNT12
LC17 -> * * * * * - - - * * * - * * * - | * * | <-- CNT11
LC18 -> * * * * * - - - * * * * * * * * | * * | <-- CNT10

Pin
43   -> * * * * * - * - - - - - - * * * | * * | <-- BUSY
6    -> * * * * * - - - - - - - * * * * | * * | <-- CLEAN
2    -> - - - - - - - - - - - - - - - - | - - | <-- CLK
4    -> * * * * * - - - - - - - * * * * | * * | <-- DOWN
5    -> * * * * * - - - - - - - * - * * | * * | <-- LEFT
8    -> * * * * * - - - - - - - * * * * | * * | <-- RIGHT
9    -> * * * * * - - - - - - - * * * * | * * | <-- UP
LC5  -> * * * * * * - * * * * * * * * * | * * | <-- CNT22
LC4  -> * * * * * * - * * * * * * * * * | * * | <-- CNT21
LC6  -> - - - * - - - - - - - - - - - - | - * | <-- ~644~1
LC2  -> * - - - - - - - - - - - - - - - | - * | <-- ~668~1
LC1  -> * - - - - - - - - - - - - - - - | - * | <-- ~668~2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        e:\作业\eda\yejing\lcd.rpt
lcd

** EQUATIONS **

BUSY     : INPUT;
CLEAN    : INPUT;
CLK      : INPUT;
DOWN     : INPUT;
LEFT     : INPUT;
RIGHT    : INPUT;
UP       : INPUT;

-- Node name is ':40' = 'CNT10' 
-- Equation name is 'CNT10', location is LC018, type is buried.
CNT10    = TFFE( _EQ001, GLOBAL( BUSY),  VCC,  VCC,  VCC);
  _EQ001 = !CNT20 & !CNT21 &  CNT22;

-- Node name is ':39' = 'CNT11' 
-- Equation name is 'CNT11', location is LC017, type is buried.
CNT11    = TFFE( _EQ002, GLOBAL( BUSY),  VCC,  VCC,  VCC);
  _EQ002 =  CNT10 & !CNT20 & !CNT21 &  CNT22;

-- Node name is ':38' = 'CNT12' 
-- Equation name is 'CNT12', location is LC019, type is buried.
CNT12    = TFFE( _EQ003, GLOBAL( BUSY),  VCC,  VCC,  VCC);
  _EQ003 =  CNT10 &  CNT11 & !CNT20 & !CNT21 &  CNT22;

-- Node name is ':37' = 'CNT13' 
-- Equation name is 'CNT13', location is LC020, type is buried.
CNT13    = TFFE( _EQ004, GLOBAL( BUSY),  VCC,  VCC,  VCC);
  _EQ004 =  CNT10 &  CNT11 &  CNT12 & !CNT20 & !CNT21 &  CNT22;

-- Node name is ':36' = 'CNT20' 
-- Equation name is 'CNT20', location is LC021, type is buried.
CNT20    = TFFE(!_EQ005, GLOBAL( BUSY),  VCC,  VCC,  VCC);
  _EQ005 = !CNT20 & !CNT21 &  CNT22;

-- Node name is ':35' = 'CNT21' 
-- Equation name is 'CNT21', location is LC004, type is buried.
CNT21    = TFFE( CNT20, GLOBAL( BUSY),  VCC,  VCC,  VCC);

-- Node name is ':34' = 'CNT22' 
-- Equation name is 'CNT22', location is LC005, type is buried.
CNT22    = DFFE( _EQ006 $  _LC025, GLOBAL( BUSY),  VCC,  VCC,  VCC);
  _EQ006 = !CNT20 & !CNT21 &  CNT22 &  _LC025;

-- Node name is 'DOUT0' = ':24' 
-- Equation name is 'DOUT0', type is output 
 DOUT0   = DFFE( _EQ007 $  VCC, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ007 = !_LC012 & !_LC014 & !_LC030;

-- Node name is 'DOUT1' = ':22' 
-- Equation name is 'DOUT1', type is output 
 DOUT1   = DFFE( _EQ008 $ !DOWN, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ008 = !_LC029 & !_LC031 &  _X001;
  _X001  = EXP( BUSY &  DOWN);

-- Node name is 'DOUT2' = ':20' 
-- Equation name is 'DOUT2', type is output 
 DOUT2   = DFFE( _EQ009 $  _EQ010, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ009 = !BUSY & !CLEAN &  CNT10 &  CNT11 &  CNT12 & !CNT20 & !CNT21 & 
             !DOWN & !_LC001 & !_LC002 & !LEFT & !UP &  _X002
         # !BUSY & !CLEAN &  CNT11 &  CNT13 &  CNT20 &  CNT21 & !DOWN & 
             !_LC001 & !_LC002 & !LEFT & !UP &  _X002
         # !BUSY & !CLEAN & !CNT10 & !CNT11 &  CNT12 &  CNT22 & !DOWN & 
             !_LC001 & !_LC002 & !LEFT & !UP &  _X002
         # !BUSY & !CLEAN &  CNT12 & !CNT13 & !CNT20 & !CNT21 & !DOWN & 
             !_LC001 & !_LC002 & !LEFT & !UP &  _X002;
  _X002  = EXP(!DOWN & !LEFT &  RIGHT & !UP);
  _EQ010 = !BUSY & !_LC001 & !_LC002 &  _X002;
  _X002  = EXP(!DOWN & !LEFT &  RIGHT & !UP);

-- Node name is 'DOUT3' = ':18' 
-- Equation name is 'DOUT3', type is output 
 DOUT3   = DFFE( _EQ011 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ011 = !BUSY & !CLEAN & !CNT10 &  CNT11 &  CNT12 &  CNT13 &  CNT20 & 
              CNT21 & !CNT22 & !DOWN & !LEFT & !UP
         # !BUSY & !CLEAN &  CNT10 &  CNT11 & !CNT12 &  CNT13 &  CNT20 & 
              CNT21 & !CNT22 & !DOWN & !LEFT & !UP
         # !BUSY & !CLEAN &  CNT10 &  CNT11 &  CNT12 & !CNT22 & !DOWN & !LEFT & 
             !UP &  _X003
         # !BUSY & !DOWN & !LEFT &  RIGHT & !UP;
  _X003  = EXP( CNT13 &  CNT20 &  CNT21);

-- Node name is 'DOUT4' = ':16' 
-- Equation name is 'DOUT4', type is output 
 DOUT4   = DFFE( _EQ012 $  _EQ013, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ012 = !BUSY & !CLEAN &  CNT11 & !CNT12 &  CNT13 &  CNT20 & !DOWN & 
             !_LC003 & !_LC032 & !LEFT & !RIGHT & !UP &  _X004
         # !BUSY & !CLEAN & !CNT10 &  CNT11 &  CNT13 &  CNT22 & !DOWN & 
             !_LC003 & !_LC032 & !LEFT & !RIGHT & !UP &  _X004
         # !BUSY & !CLEAN &  CNT10 & !CNT11 &  CNT13 &  CNT22 & !DOWN & 
             !_LC003 & !_LC032 & !LEFT & !RIGHT & !UP &  _X004
         # !BUSY & !CLEAN & !CNT10 & !CNT11 & !CNT12 &  CNT22 & !DOWN & 
             !_LC003 & !_LC032 & !LEFT & !RIGHT & !UP &  _X004;
  _X004  = EXP(!CLEAN &  CNT20 & !CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
  _EQ013 = !BUSY & !_LC003 & !_LC032 &  _X004;
  _X004  = EXP(!CLEAN &  CNT20 & !CNT21 & !DOWN & !LEFT & !RIGHT & !UP);

-- Node name is 'DOUT5' = ':14' 
-- Equation name is 'DOUT5', type is output 
 DOUT5   = DFFE( _EQ014 $  _EQ015, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ014 = !BUSY & !CLEAN &  CNT10 &  CNT11 &  CNT12 &  CNT22 & !DOWN & !LEFT & 
             !RIGHT & !UP &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 & 
              _X009 &  _X010
         # !BUSY & !CLEAN &  CNT10 & !CNT12 &  CNT13 &  CNT20 & !DOWN & !LEFT & 
             !RIGHT & !UP &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 & 
              _X009 &  _X010
         # !BUSY & !CLEAN & !CNT10 & !CNT11 &  CNT12 &  CNT20 & !DOWN & !LEFT & 
             !RIGHT & !UP &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 & 
              _X009 &  _X010
         # !BUSY & !CLEAN & !CNT11 & !CNT13 &  CNT21 & !DOWN & !LEFT & !RIGHT & 
             !UP &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 & 
              _X010;
  _X004  = EXP(!CLEAN &  CNT20 & !CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
  _X005  = EXP(!CLEAN &  CNT20 &  CNT22 & !DOWN & !LEFT & !RIGHT & !UP);
  _X006  = EXP(!CLEAN & !CNT20 &  CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
  _X007  = EXP(!CLEAN & !CNT10 & !CNT13 &  CNT21 & !DOWN & !LEFT & !RIGHT & !UP);
  _X008  = EXP(!CLEAN & !CNT10 & !CNT11 &  CNT22 & !DOWN & !LEFT & !RIGHT & !UP);

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