count60.rpt

用chdl编写液晶块驱动程序。有详细的说明

Device-Specific Information:                    e:\作业\eda\yejing\count60.rpt
count60

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (32)    25    B       SOFT      t        0      0   0    0    3    1    0  |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node2
 (38)    20    B       SOFT      t        0      0   0    0    6    1    0  |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node5


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                    e:\作业\eda\yejing\count60.rpt
count60

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC21 CO
        | +--------------- LC24 DOUT0
        | | +------------- LC17 DOUT1
        | | | +----------- LC19 DOUT2
        | | | | +--------- LC18 DOUT3
        | | | | | +------- LC22 DOUT4
        | | | | | | +----- LC23 DOUT5
        | | | | | | | +--- LC25 |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node2
        | | | | | | | | +- LC20 |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node5
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> * - - - - - - - - | - * | <-- CO
LC24 -> * * * * * * * * * | - * | <-- DOUT0
LC17 -> * - * * * * * * * | - * | <-- DOUT1
LC19 -> * - - * * * * * * | - * | <-- DOUT2
LC18 -> * - - * * * * - * | - * | <-- DOUT3
LC22 -> * - - * * * * - * | - * | <-- DOUT4
LC23 -> * - - * * * * - * | - * | <-- DOUT5
LC25 -> - - - * - - - - - | - * | <-- |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node2
LC20 -> - - - - - - * - - | - * | <-- |LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node5

Pin
43   -> - - - - - - - - - | - - | <-- CLK
4    -> * * * * * * * - - | - * | <-- EN


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                    e:\作业\eda\yejing\count60.rpt
count60

** EQUATIONS **

CLK      : INPUT;
EN       : INPUT;

-- Node name is 'CO' = ':2' 
-- Equation name is 'CO', type is output 
 CO      = DFFE( _EQ001 $  GND, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ001 =  DOUT0 &  DOUT1 & !DOUT2 &  DOUT3 &  DOUT4 &  DOUT5 &  EN
         #  CO & !EN;

-- Node name is 'DOUT0' = 'CNT0' 
-- Equation name is 'DOUT0', location is LC024, type is output.
 DOUT0   = TFFE( EN, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is 'DOUT1' = 'CNT1' 
-- Equation name is 'DOUT1', location is LC017, type is output.
 DOUT1   = TFFE( _EQ002, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ002 =  DOUT0 &  EN;

-- Node name is 'DOUT2' = 'CNT2' 
-- Equation name is 'DOUT2', location is LC019, type is output.
 DOUT2   = DFFE( _EQ003 $  _LC025, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ003 =  DOUT0 &  DOUT1 & !DOUT2 &  DOUT3 &  DOUT4 &  DOUT5 &  _LC025
         #  DOUT2 & !EN & !_LC025
         # !DOUT2 & !EN &  _LC025;

-- Node name is 'DOUT3' = 'CNT3' 
-- Equation name is 'DOUT3', location is LC018, type is output.
 DOUT3   = TFFE( _EQ004, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ004 =  DOUT0 &  DOUT1 & !DOUT2 &  DOUT3 &  DOUT4 &  DOUT5 &  EN
         #  DOUT0 &  DOUT1 &  DOUT2 &  EN;

-- Node name is 'DOUT4' = 'CNT4' 
-- Equation name is 'DOUT4', location is LC022, type is output.
 DOUT4   = TFFE( _EQ005, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ005 =  DOUT0 &  DOUT1 & !DOUT2 &  DOUT3 &  DOUT4 &  DOUT5 &  EN
         #  DOUT0 &  DOUT1 &  DOUT2 &  DOUT3 &  EN;

-- Node name is 'DOUT5' = 'CNT5' 
-- Equation name is 'DOUT5', location is LC023, type is output.
 DOUT5   = DFFE( _EQ006 $  _LC020, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ006 =  DOUT0 &  DOUT1 & !DOUT2 &  DOUT3 &  DOUT4 &  DOUT5 &  EN & 
              _LC020
         #  DOUT5 & !EN & !_LC020
         # !DOUT5 & !EN &  _LC020;

-- Node name is '|LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( DOUT2 $  _EQ007);
  _EQ007 =  DOUT0 &  DOUT1;

-- Node name is '|LPM_ADD_SUB:86|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( DOUT5 $  _EQ008);
  _EQ008 =  DOUT0 &  DOUT1 &  DOUT2 &  DOUT3 &  DOUT4;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             e:\作业\eda\yejing\count60.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,323K