📄 dianziz.rpt
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Pin
43 -> - - - - - - - - - - | - - | <-- CLK
LC31 -> * * * * * * * * * * | * - | <-- DOUT10
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\作业\eda\yejing\dianziz.rpt
dianziz
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC31 DOUT10
| +----------------------------- LC18 DOUT20
| | +--------------------------- LC17 DOUT21
| | | +------------------------- LC22 DOUT22
| | | | +----------------------- LC19 DOUT23
| | | | | +--------------------- LC21 DOUT24
| | | | | | +------------------- LC23 DOUT25
| | | | | | | +----------------- LC30 DOUT30
| | | | | | | | +--------------- LC29 DOUT31
| | | | | | | | | +------------- LC28 DOUT32
| | | | | | | | | | +----------- LC27 DOUT33
| | | | | | | | | | | +--------- LC26 DOUT34
| | | | | | | | | | | | +------- LC24 |LPM_ADD_SUB:327|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | | | | +----- LC25 |LPM_ADD_SUB:327|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | | | | | +--- LC32 |LPM_ADD_SUB:559|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | | | | | +- LC20 C1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC18 -> - * * * * * * - - - - - * * - * | - * | <-- DOUT20
LC17 -> - - * * * * * - - - - - * * - * | - * | <-- DOUT21
LC22 -> - - - * * * * - - - - - * * - * | - * | <-- DOUT22
LC19 -> - - - * * * * - - - - - - * - * | - * | <-- DOUT23
LC21 -> - - - * * * * - - - - - - * - * | - * | <-- DOUT24
LC23 -> - - - * * * * - - - - - - * - * | - * | <-- DOUT25
LC30 -> - - - - - - - * * * * * - - * - | - * | <-- DOUT30
LC29 -> - - - - - - - - * * * * - - * - | - * | <-- DOUT31
LC28 -> - - - - - - - - - * * * - - * - | - * | <-- DOUT32
LC27 -> - - - - - - - - - - * * - - * - | - * | <-- DOUT33
LC26 -> - - - - - - - - - - * * - - - - | - * | <-- DOUT34
LC24 -> - - - * - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:327|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:327|addcore:adder|addcore:adder0|result_node5
LC32 -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:559|addcore:adder|addcore:adder0|result_node3
LC20 -> - - - - - - - * * * * * - - - * | - * | <-- C1
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CLK
LC3 -> - * * * * * * - - - - - - - - * | - * | <-- C0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\作业\eda\yejing\dianziz.rpt
dianziz
** EQUATIONS **
CLK : INPUT;
-- Node name is ':26' = 'C0'
-- Equation name is 'C0', location is LC003, type is buried.
C0 = DFFE( _EQ001 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = DOUT10 & DOUT11 & !DOUT12 & DOUT13 & DOUT14 & DOUT15;
-- Node name is ':33' = 'C1'
-- Equation name is 'C1', location is LC020, type is buried.
C1 = DFFE( _EQ002 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = C0 & DOUT20 & DOUT21 & !DOUT22 & DOUT23 & DOUT24 & DOUT25
# !C0 & C1;
-- Node name is 'DOUT10' = 'CNT10'
-- Equation name is 'DOUT10', location is LC031, type is output.
DOUT10 = TFFE( VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'DOUT11' = 'CNT11'
-- Equation name is 'DOUT11', location is LC008, type is output.
DOUT11 = TFFE( DOUT10, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'DOUT12' = 'CNT12'
-- Equation name is 'DOUT12', location is LC006, type is output.
DOUT12 = DFFE( _EQ003 $ _LC007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = DOUT10 & DOUT11 & !DOUT12 & DOUT13 & DOUT14 & DOUT15 &
_LC007;
-- Node name is 'DOUT13' = 'CNT13'
-- Equation name is 'DOUT13', location is LC005, type is output.
DOUT13 = DFFE( _EQ004 $ _LC004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = DOUT10 & DOUT11 & !DOUT12 & DOUT13 & DOUT14 & DOUT15 &
_LC004;
-- Node name is 'DOUT14' = 'CNT14'
-- Equation name is 'DOUT14', location is LC002, type is output.
DOUT14 = DFFE( _EQ005 $ _LC012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = DOUT10 & DOUT11 & !DOUT12 & DOUT13 & DOUT14 & DOUT15 &
_LC012;
-- Node name is 'DOUT15' = 'CNT15'
-- Equation name is 'DOUT15', location is LC001, type is output.
DOUT15 = DFFE( _EQ006 $ _LC016, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = DOUT10 & DOUT11 & !DOUT12 & DOUT13 & DOUT14 & DOUT15 &
_LC016;
-- Node name is 'DOUT20' = 'CNT20'
-- Equation name is 'DOUT20', location is LC018, type is output.
DOUT20 = TFFE( C0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'DOUT21' = 'CNT21'
-- Equation name is 'DOUT21', location is LC017, type is output.
DOUT21 = TFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = C0 & DOUT20;
-- Node name is 'DOUT22' = 'CNT22'
-- Equation name is 'DOUT22', location is LC022, type is output.
DOUT22 = DFFE( _EQ008 $ _LC024, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = DOUT20 & DOUT21 & !DOUT22 & DOUT23 & DOUT24 & DOUT25 &
_LC024
# !C0 & DOUT22 & !_LC024
# !C0 & !DOUT22 & _LC024;
-- Node name is 'DOUT23' = 'CNT23'
-- Equation name is 'DOUT23', location is LC019, type is output.
DOUT23 = TFFE( _EQ009, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = C0 & DOUT20 & DOUT21 & !DOUT22 & DOUT23 & DOUT24 & DOUT25
# C0 & DOUT20 & DOUT21 & DOUT22;
-- Node name is 'DOUT24' = 'CNT24'
-- Equation name is 'DOUT24', location is LC021, type is output.
DOUT24 = TFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = C0 & DOUT20 & DOUT21 & !DOUT22 & DOUT23 & DOUT24 & DOUT25
# C0 & DOUT20 & DOUT21 & DOUT22 & DOUT23;
-- Node name is 'DOUT25' = 'CNT25'
-- Equation name is 'DOUT25', location is LC023, type is output.
DOUT25 = DFFE( _EQ011 $ _LC025, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = C0 & DOUT20 & DOUT21 & !DOUT22 & DOUT23 & DOUT24 & DOUT25 &
_LC025
# !C0 & DOUT25 & !_LC025
# !C0 & !DOUT25 & _LC025;
-- Node name is 'DOUT30' = 'CNT30'
-- Equation name is 'DOUT30', location is LC030, type is output.
DOUT30 = TFFE( C1, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'DOUT31' = 'CNT31'
-- Equation name is 'DOUT31', location is LC029, type is output.
DOUT31 = TFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = C1 & DOUT30;
-- Node name is 'DOUT32' = 'CNT32'
-- Equation name is 'DOUT32', location is LC028, type is output.
DOUT32 = TFFE( _EQ013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = C1 & DOUT30 & DOUT31;
-- Node name is 'DOUT33' = 'CNT33'
-- Equation name is 'DOUT33', location is LC027, type is output.
DOUT33 = DFFE( _EQ014 $ _LC032, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = DOUT30 & DOUT31 & DOUT32 & !DOUT33 & DOUT34 & _LC032
# !C1 & DOUT33 & !_LC032
# !C1 & !DOUT33 & _LC032;
-- Node name is 'DOUT34' = 'CNT34'
-- Equation name is 'DOUT34', location is LC026, type is output.
DOUT34 = TFFE( _EQ015, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = C1 & DOUT30 & DOUT31 & DOUT32 & !DOUT33 & DOUT34
# C1 & DOUT30 & DOUT31 & DOUT32 & DOUT33;
-- Node name is '|LPM_ADD_SUB:142|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC007', type is buried
_LC007 = LCELL( DOUT12 $ _EQ016);
_EQ016 = DOUT10 & DOUT11;
-- Node name is '|LPM_ADD_SUB:142|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( DOUT13 $ _EQ017);
_EQ017 = DOUT10 & DOUT11 & DOUT12;
-- Node name is '|LPM_ADD_SUB:142|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried
_LC012 = LCELL( DOUT14 $ _EQ018);
_EQ018 = DOUT10 & DOUT11 & DOUT12 & DOUT13;
-- Node name is '|LPM_ADD_SUB:142|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC016', type is buried
_LC016 = LCELL( DOUT15 $ _EQ019);
_EQ019 = DOUT10 & DOUT11 & DOUT12 & DOUT13 & DOUT14;
-- Node name is '|LPM_ADD_SUB:327|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( DOUT22 $ _EQ020);
_EQ020 = DOUT20 & DOUT21;
-- Node name is '|LPM_ADD_SUB:327|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( DOUT25 $ _EQ021);
_EQ021 = DOUT20 & DOUT21 & DOUT22 & DOUT23 & DOUT24;
-- Node name is '|LPM_ADD_SUB:559|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( DOUT33 $ _EQ022);
_EQ022 = DOUT30 & DOUT31 & DOUT32;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\作业\eda\yejing\dianziz.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,818K
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