📄 dianziz.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY DIANZIZ IS
PORT(CLK:IN STD_LOGIC;
BUSY:IN STD_LOGIC;
DOUT1:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
DOUT2:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
DOUT3:OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END ENTITY;
ARCHITECTURE RAT OF DIANZIZ IS
COMPONENT COUNT60 IS
PORT(EN:STD_LOGIC;
CO:STD_LOGIC;
DOUT:STD_LOGIC_VECTOR(5 DOWNTO 0));
BEGIN
PROCESS(CLK)
BEGIN
END ARCHITECTURE;
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