📄 k0r_sfr_set.c
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/***************************************************************************************************************
;
; NNNNNN NN EEEEEEEEEEEEEEEEEE CCCCCCCCCCCCCCC
; NNNNNNNN NN EEEEEE CCCCCC
; NNNNNNNNNN NN EEEEEE CCCCCC
; NN NNNNNNNN NN EEEEEEEEEEEEEEEEE CCCCCC
; NN NNNNNNNN NN EEEEEE CCCCCC
; NN NNNNNNNNNN EEEEEE CCCCCC
; NN NNNNNN EEEEEEEEEEEEEEEE CCCCCCCCCCCCCCC
;
; NEC Electronics 78K0R/Kx3 Series
;丂丂
;亂License Agreement亃
;. This sample program is subject to change without notice.
;
;. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
; property rights of third parties by or arising from the use of this sample program. No license, express,
; implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of
; NEC Electronics or others.
;
;. Descriptions of commands, program, and other related information in this sample program are provided for
; illustrative purposes in semiconductor product operation and application examples. The incorporation of
; this sample program in the design of a customer's equipment shall be done under the full responsibility of
; the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties
; arising from the use of this sample program.
;
;丂Please use this sample program under the agreement listed above.
;
;***************************************************************************************************************
; 78K0R/Kx3 Series sample program
;***************************************************************************************************************
; A/D Converter (SFR Setting)
;***************************************************************************************************************
; [History]
; 2007.07 new
;***************************************************************************************************************/
/***************************************************************************
* Title: SFR setting
***************************************************************************
* Condition:
* device: uPD78F1166
* AVREF0 = 5V
* analog input: ANI14/P156, ANI15/P157
* digital input: ANI0/P20-ANI13/P155
***************************************************************************/
#pragma sfr /* definition for using SFR */
#pragma NOP /* definition for using NOP */
void SAD_INIT(void);
void SAD_CSTT(void);
void SAD_CSTP(void);
/***************************************************************************
* variable declaration
***************************************************************************/
unsigned int AD_VALUE; /* A/D conversion result */
/***************************************************************************
* Title: initial setting of A/D converter
****************************************************************************
* Module: void SAD_INIT(void)
* Arg:
* Ret:
***************************************************************************/
void SAD_INIT(void)
{
ADCEN = 1; /* supplies input clock to A/D converter */
ADCE = 1; /* enables comparator operation */
ADPC = 0b00001110; /* A/D port configuration
analog input: ANI14/P156, ANI15/P157
digital input: ANI0/P20-ANI13/P155 */
/**************************************************
port initial setting */
PM2 = 0b00000000; /* P20-P27: output mode */
PM15 = 0b11000000; /* ANI15/P157 & ANI14/P156: input mode */
/**************************************************
A/D conversion mode register */
ADM = 0b00000001; /* ADCS=0: stops conversion operation
FR2=FR1=FR0=LV1=LV0=0: conversion time = 264/fCLK @20MHz
ADCE=1: enables comparator operation */
ADS = 0x0e; /* analog input channel: ANI14/P156 */
ADCS = 1; /* enables conversion operation */
ADIF = 0; /* clear interrupt request flag of INTAD */
while(ADIF == 0); /* wait until A/D conversion completes */
AD_VALUE = ADCR; /* get A/D conversion result (16-bit with lower 6-bit '0') */
}
/***************************************************************************
* Title: channel change (ANI14 --> ANI15)
****************************************************************************
* Module: void SAD_CHAN(void)
* Arg:
* Ret:
***************************************************************************/
void SAD_CHAN(void)
{
ADS = 0x0f; /* analog input channel: ANI15/P157 */
ADCS = 1; /* enables conversion operation */
ADIF = 0; /* clear interrupt request flag of INTAD */
while(ADIF == 0); /* wait until A/D conversion completes */
AD_VALUE = ADCRH; /* get A/D conversion result (16-bit with lower 6-bit '0') */
}
/***************************************************************************
* Title: A/D conversion operation stop
****************************************************************************
* Module: void SAD_STOP(void)
* Arg:
* Ret:
***************************************************************************/
void SAD_STOP(void)
{
ADCS = 0; /* stops conversion operation */
ADCE = 0; /* stops comparator operation */
ADCEN = 0; /* stops supply of input clock */
}
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