📄 s2440addr.inc
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;====================================================================
; File Name : 2440addr.a
; Function : S3C2440 Define Address Register (Assembly)
; Program : Shin, On Pil (SOP)
; Date : March 27, 2002
; Version : 0.0
; History
; 0.0 : Programming start (February 18,2002) -> SOP
;====================================================================
GBLL BIG_ENDIAN__
BIG_ENDIAN__ SETL {FALSE}
;=================
; Memory control
;=================
BWSCON EQU 0x48000000 ;Bus width & wait status
BANKCON0 EQU 0x48000004 ;Boot ROM control
BANKCON1 EQU 0x48000008 ;BANK1 control
BANKCON2 EQU 0x4800000c ;BANK2 cControl
BANKCON3 EQU 0x48000010 ;BANK3 control
BANKCON4 EQU 0x48000014 ;BANK4 control
BANKCON5 EQU 0x48000018 ;BANK5 control
BANKCON6 EQU 0x4800001c ;BANK6 control
BANKCON7 EQU 0x48000020 ;BANK7 control
REFRESH EQU 0x48000024 ;DRAM/SDRAM refresh
BANKSIZE EQU 0x48000028 ;Flexible Bank Size
MRSRB6 EQU 0x4800002c ;Mode register set for SDRAM
MRSRB7 EQU 0x48000030 ;Mode register set for SDRAM
;=================
; USB Host
;=================
;=================
; INTERRUPT
;=================
SRCPND EQU 0x4a000000 ;Interrupt request status
INTMOD EQU 0x4a000004 ;Interrupt mode control
INTMSK EQU 0x4a000008 ;Interrupt mask control
PRIORITY EQU 0x4a00000a ;IRQ priority control
INTPND EQU 0x4a000010 ;Interrupt request status
INTOFFSET EQU 0x4a000014 ;Interruot request source offset
SUSSRCPND EQU 0x4a000018 ;Sub source pending
INTSUBMSK EQU 0x4a00001c ;Interrupt sub mask
;=================
; DMA
;=================
DISRC0 EQU 0x4b000000 ;DMA 0 Initial source
DISRCC0 EQU 0x4b000004 ;DMA 0 Initial source control
DIDST0 EQU 0x4b000008 ;DMA 0 Initial Destination
DIDSTC0 EQU 0x4b00000c ;DMA 0 Initial Destination control
DCON0 EQU 0x4b000010 ;DMA 0 Control
DSTAT0 EQU 0x4b000014 ;DMA 0 Status
DCSRC0 EQU 0x4b000018 ;DMA 0 Current source
DCDST0 EQU 0x4b00001c ;DMA 0 Current destination
DMASKTRIG0 EQU 0x4b000020 ;DMA 0 Mask trigger
DISRC1 EQU 0x4b000040 ;DMA 1 Initial source
DISRCC1 EQU 0x4b000044 ;DMA 1 Initial source control
DIDST1 EQU 0x4b000048 ;DMA 1 Initial Destination
DIDSTC1 EQU 0x4b00004c ;DMA 1 Initial Destination control
DCON1 EQU 0x4b000050 ;DMA 1 Control
DSTAT1 EQU 0x4b000054 ;DMA 1 Status
DCSRC1 EQU 0x4b000058 ;DMA 1 Current source
DCDST1 EQU 0x4b00005c ;DMA 1 Current destination
DMASKTRIG1 EQU 0x4b000060 ;DMA 1 Mask trigger
DISRC2 EQU 0x4b000080 ;DMA 2 Initial source
DISRCC2 EQU 0x4b000084 ;DMA 2 Initial source control
DIDST2 EQU 0x4b000088 ;DMA 2 Initial Destination
DIDSTC2 EQU 0x4b00008c ;DMA 2 Initial Destination control
DCON2 EQU 0x4b000090 ;DMA 2 Control
DSTAT2 EQU 0x4b000094 ;DMA 2 Status
DCSRC2 EQU 0x4b000098 ;DMA 2 Current source
DCDST2 EQU 0x4b00009c ;DMA 2 Current destination
DMASKTRIG2 EQU 0x4b0000a0 ;DMA 2 Mask trigger
DISRC3 EQU 0x4b0000c0 ;DMA 3 Initial source
DISRCC3 EQU 0x4b0000c4 ;DMA 3 Initial source control
DIDST3 EQU 0x4b0000c8 ;DMA 3 Initial Destination
DIDSTC3 EQU 0x4b0000cc ;DMA 3 Initial Destination control
DCON3 EQU 0x4b0000d0 ;DMA 3 Control
DSTAT3 EQU 0x4b0000d4 ;DMA 3 Status
DCSRC3 EQU 0x4b0000d8 ;DMA 3 Current source
DCDST3 EQU 0x4b0000dc ;DMA 3 Current destination
DMASKTRIG3 EQU 0x4b0000e0 ;DMA 3 Mask trigger
;==========================
; CLOCK & POWER MANAGEMENT
;==========================
LOCKTIME EQU 0x4c000000 ;PLL lock time counter
MPLLCON EQU 0x4c000004 ;MPLL Control
UPLLCON EQU 0x4c000008 ;UPLL Control
CLKCON EQU 0x4c00000c ;Clock generator control
CLKSLOW EQU 0x4c000010 ;Slow clock control
CLKDIVN EQU 0x4c000014 ;Clock divider control
CAMDIVN EQU 0x4c000018 ;Camera control
;=================
; LCD CONTROLLER
;=================
LCDCON1 EQU 0x4d000000 ;LCD control 1
LCDCON2 EQU 0x4d000004 ;LCD control 2
LCDCON3 EQU 0x4d000008 ;LCD control 3
LCDCON4 EQU 0x4d00000c ;LCD control 4
LCDCON5 EQU 0x4d000010 ;LCD control 5
LCDSADDR1 EQU 0x4d000014 ;STN/TFT Frame buffer start address 1
LCDSADDR2 EQU 0x4d000018 ;STN/TFT Frame buffer start address 2
LCDSADDR3 EQU 0x4d00001c ;STN/TFT Virtual screen address set
REDLUT EQU 0x4d000020 ;STN Red lookup table
GREENLUT EQU 0x4d000024 ;STN Green lookup table
BLUELUT EQU 0x4d000028 ;STN Blue lookup table
DITHMODE EQU 0x4d00004c ;STN Dithering mode
TPAL EQU 0x4d000050 ;TFT Temporary palette
LCDINTPND EQU 0x4d000054 ;LCD Interrupt pending
LCDSRCPND EQU 0x4d000058 ;LCD Interrupt source
LCDINTMSK EQU 0x4d00005c ;LCD Interrupt mask
TCONSEL EQU 0x4d000060 ;LPC3600 Control
;=================
; NAND flash
;=================
;NFCONF EQU 0x4e000000 ;NAND Flash configuration
;NFCMD EQU 0x4e000004 ;NADD Flash command
;NFADDR EQU 0x4e000008 ;NAND Flash address
;NFDATA EQU 0x4e00000c ;NAND Flash data
;NFSTAT EQU 0x4e000010 ;NAND Flash operation status
;NFECC EQU 0x4e000014 ;NAND Flash ECC
NFCONF EQU 0x4E000000
NFCONT EQU 0x4E000004
NFCMD EQU 0x4E000008
NFADDR EQU 0x4E00000C
NFDATA EQU 0x4E000010
NFMECCD0 EQU 0x4E000014
NFMECCD1 EQU 0x4E000018
NFSECCD EQU 0x4E00001C
NFSTAT EQU 0x4e000020 ; NAND Flash operation status
NFESTAT0 EQU 0x4e000024
NFESTAT1 EQU 0x4e000028
NFMECC0 EQU 0x4e00002C
NFMECC1 EQU 0x4e000030
NFSECC EQU 0x4e000034
NFSBLK EQU 0x4e000038
NFEBLK EQU 0x4e00003C
;=================
; Camera Interface
;=================
CISRCFMT EQU 0x4f000000
CIWDOFST EQU 0x4f000004
CIGCTRL EQU 0x4f000008
PAD1 EQU 0x4f00000c
PAD2 EQU 0x4f000010
PAD3 EQU 0x4f000014
CICOYSA1 EQU 0x4f000018
CICOYSA2 EQU 0x4f00001c
CICOYSA3 EQU 0x4f000020
CICOYSA4 EQU 0x4f000024
CICOCBSA1 EQU 0x4f000028
CICOCBSA2 EQU 0x4f00002c
CICOCBSA3 EQU 0x4f000030
CICOCBSA4 EQU 0x4f000034
CICOCRSA1 EQU 0x4f000038
CICOCRSA2 EQU 0x4f00003c
CICOCRSA3 EQU 0x4f000040
CICOCRSA4 EQU 0x4f000044
CICOTRGFMT EQU 0x4f000048
CICOCTRL EQU 0x4f00004c
CICOSCPRERATIO EQU 0x4f000050
CICOSCPREDST EQU 0x4f000054
CICOSCCTRL EQU 0x4f000058
CICOTAREA EQU 0x4f00005c
PAD4 EQU 0x4f000060
CICOSTATUS EQU 0x4f000064
PAD5 EQU 0x4f000068
CIPRCLRSA1 EQU 0x4f00006c
CIPRCLRSA2 EQU 0x4f000070
CIPRCLRSA3 EQU 0x4f000074
CIPRCLRSA4 EQU 0x4f000078
CIPRTRGFMT EQU 0x4f00007c
CIPRCTRL EQU 0x4f000080
CIPRSCPRERATIO EQU 0x4f000084
CIPRSCPREDST EQU 0x4f000088
CIPRSCCTRL EQU 0x4f00008c
CIPRTAREA EQU 0x4f000090
PAD6 EQU 0x4f000094
CIPRSTATUS EQU 0x4f000098
PAD7 EQU 0x4f00009c
CIIMGCPT EQU 0x4f0000a0
;=================
; UART
;=================
ULCON0 EQU 0x50000000 ;UART 0 Line control
UCON0 EQU 0x50000004 ;UART 0 Control
UFCON0 EQU 0x50000008 ;UART 0 FIFO control
UMCON0 EQU 0x5000000c ;UART 0 Modem control
UTRSTAT0 EQU 0x50000010 ;UART 0 Tx/Rx status
UERSTAT0 EQU 0x50000014 ;UART 0 Rx error status
UFSTAT0 EQU 0x50000018 ;UART 0 FIFO status
UMSTAT0 EQU 0x5000001c ;UART 0 Modem status
UBRDIV0 EQU 0x50000028 ;UART 0 Baud rate divisor
ULCON1 EQU 0x50004000 ;UART 1 Line control
UCON1 EQU 0x50004004 ;UART 1 Control
UFCON1 EQU 0x50004008 ;UART 1 FIFO control
UMCON1 EQU 0x5000400c ;UART 1 Modem control
UTRSTAT1 EQU 0x50004010 ;UART 1 Tx/Rx status
UERSTAT1 EQU 0x50004014 ;UART 1 Rx error status
UFSTAT1 EQU 0x50004018 ;UART 1 FIFO status
UMSTAT1 EQU 0x5000401c ;UART 1 Modem status
UBRDIV1 EQU 0x50004028 ;UART 1 Baud rate divisor
ULCON2 EQU 0x50008000 ;UART 2 Line control
UCON2 EQU 0x50008004 ;UART 2 Control
UFCON2 EQU 0x50008008 ;UART 2 FIFO control
UMCON2 EQU 0x5000800c ;UART 2 Modem control
UTRSTAT2 EQU 0x50008010 ;UART 2 Tx/Rx status
UERSTAT2 EQU 0x50008014 ;UART 2 Rx error status
UFSTAT2 EQU 0x50008018 ;UART 2 FIFO status
UMSTAT2 EQU 0x5000801c ;UART 2 Modem status
UBRDIV2 EQU 0x50008028 ;UART 2 Baud rate divisor
[ BIG_ENDIAN__
UTXH0 EQU 0x50000023 ;UART 0 Transmission Hold
URXH0 EQU 0x50000027 ;UART 0 Receive buffer
UTXH1 EQU 0x50004023 ;UART 1 Transmission Hold
URXH1 EQU 0x50004027 ;UART 1 Receive buffer
UTXH2 EQU 0x50008023 ;UART 2 Transmission Hold
URXH2 EQU 0x50008027 ;UART 2 Receive buffer
| ;Little Endian
UTXH0 EQU 0x50000020 ;UART 0 Transmission Hold
URXH0 EQU 0x50000024 ;UART 0 Receive buffer
UTXH1 EQU 0x50004020 ;UART 1 Transmission Hold
URXH1 EQU 0x50004024 ;UART 1 Receive buffer
UTXH2 EQU 0x50008020 ;UART 2 Transmission Hold
URXH2 EQU 0x50008024 ;UART 2 Receive buffer
]
;=================
; PWM TIMER
;=================
TCFG0 EQU 0x51000000 ;Timer 0 configuration
TCFG1 EQU 0x51000004 ;Timer 1 configuration
TCON EQU 0x51000008 ;Timer control
TCNTB0 EQU 0x5100000c ;Timer count buffer 0
TCMPB0 EQU 0x51000010 ;Timer compare buffer 0
TCNTO0 EQU 0x51000014 ;Timer count observation 0
TCNTB1 EQU 0x51000018 ;Timer count buffer 1
TCMPB1 EQU 0x5100001c ;Timer compare buffer 1
TCNTO1 EQU 0x51000020 ;Timer count observation 1
TCNTB2 EQU 0x51000024 ;Timer count buffer 2
TCMPB2 EQU 0x51000028 ;Timer compare buffer 2
TCNTO2 EQU 0x5100002c ;Timer count observation 2
TCNTB3 EQU 0x51000030 ;Timer count buffer 3
TCMPB3 EQU 0x51000034 ;Timer compare buffer 3
TCNTO3 EQU 0x51000038 ;Timer count observation 3
TCNTB4 EQU 0x5100003c ;Timer count buffer 4
TCNTO4 EQU 0x51000040 ;Timer count observation 4
;=================
; USB DEVICE
;=================
[ BIG_ENDIAN__
FUNC_ADDR_REG EQU 0x52000143 ;Function address
PWR_REG EQU 0x52000147 ;Power management
EP_INT_REG EQU 0x5200014b ;EP Interrupt pending and clear
USB_INT_REG EQU 0x5200015b ;USB Interrupt pending and clear
EP_INT_EN_REG EQU 0x5200015f ;Interrupt enable
USB_INT_EN_REG EQU 0x5200016f
FRAME_NUM1_REG EQU 0x52000173 ;Frame number lower byte
FRAME_NUM2_REG EQU 0x52000177 ;Frame number lower byte
INDEX_REG EQU 0x5200017b ;Register index
MAXP_REG EQU 0x52000183 ;Endpoint max packet
EP0_CSR EQU 0x52000187 ;Endpoint 0 status
IN_CSR1_REG EQU 0x52000187 ;In endpoint control status
IN_CSR2_REG EQU 0x5200018b
OUT_CSR1_REG EQU 0x52000193 ;Out endpoint control status
OUT_CSR2_REG EQU 0x52000197
OUT_FIFO_CNT1_REG EQU 0x5200019b ;Endpoint out write count
OUT_FIFO_CNT2_REG EQU 0x5200019f
EP0_FIFO EQU 0x520001c3 ;Endpoint 0 FIFO
EP1_FIFO EQU 0x520001c7 ;Endpoint 1 FIFO
EP2_FIFO EQU 0x520001cb ;Endpoint 2 FIFO
EP3_FIFO EQU 0x520001cf ;Endpoint 3 FIFO
EP4_FIFO EQU 0x520001d3 ;Endpoint 4 FIFO
EP1_DMA_CON EQU 0x52000203 ;EP1 DMA interface control
EP1_DMA_UNIT EQU 0x52000207 ;EP1 DMA Tx unit counter
EP1_DMA_FIFO EQU 0x5200020b ;EP1 DMA Tx FIFO counter
EP1_DMA_TTC_L EQU 0x5200020f ;EP1 DMA total Tx counter
EP1_DMA_TTC_M EQU 0x52000213
EP1_DMA_TTC_H EQU 0x52000217
EP2_DMA_CON EQU 0x5200021b ;EP2 DMA interface control
EP2_DMA_UNIT EQU 0x5200021f ;EP2 DMA Tx unit counter
EP2_DMA_FIFO EQU 0x52000223 ;EP2 DMA Tx FIFO counter
EP2_DMA_TTC_L EQU 0x52000227 ;EP2 DMA total Tx counter
EP2_DMA_TTC_M EQU 0x5200022b
EP2_DMA_TTC_H EQU 0x5200022f
EP3_DMA_CON EQU 0x52000243 ;EP3 DMA interface control
EP3_DMA_UNIT EQU 0x52000247 ;EP3 DMA Tx unit counter
EP3_DMA_FIFO EQU 0x5200024b ;EP3 DMA Tx FIFO counter
EP3_DMA_TTC_L EQU 0x5200024f ;EP3 DMA total Tx counter
EP3_DMA_TTC_M EQU 0x52000253
EP3_DMA_TTC_H EQU 0x52000257
EP4_DMA_CON EQU 0x5200025b ;EP4 DMA interface control
EP4_DMA_UNIT EQU 0x5200025f ;EP4 DMA Tx unit counter
EP4_DMA_FIFO EQU 0x52000263 ;EP4 DMA Tx FIFO counter
EP4_DMA_TTC_L EQU 0x52000267 ;EP4 DMA total Tx counter
EP4_DMA_TTC_M EQU 0x5200026b
EP4_DMA_TTC_H EQU 0x5200026f
| ; Little Endian
FUNC_ADDR_REG EQU 0x52000140 ;Function address
PWR_REG EQU 0x52000144 ;Power management
EP_INT_REG EQU 0x52000148 ;EP Interrupt pending and clear
USB_INT_REG EQU 0x52000158 ;USB Interrupt pending and clear
EP_INT_EN_REG EQU 0x5200015c ;Interrupt enable
USB_INT_EN_REG EQU 0x5200016c
FRAME_NUM1_REG EQU 0x52000170 ;Frame number lower byte
FRAME_NUM2_REG EQU 0x52000174 ;Frame number lower byte
INDEX_REG EQU 0x52000178 ;Register index
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