📄 startup.s
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30 ldr r2, [r1], #4 ; (r2) = virtual address to map Bank at
ldr r3, [r1], #4 ; (r3) = physical address to map from
ldr r4, [r1], #4 ; (r4) = num MB to map
cmp r4, #0 ; End of table?
beq %f40
ldr r5, =0x1FF00000
and r2, r2, r5 ; VA needs 512MB, 1MB aligned.
ldr r5, =0xFFF00000
and r3, r3, r5 ; PA needs 4GB, 1MB aligned.
add r2, r10, r2, LSR #18
add r0, r0, r3 ; (r0) = PTE for next physical page
35 str r0, [r2], #4
add r0, r0, #0x00100000 ; (r0) = PTE for next physical page
sub r4, r4, #1 ; Decrement number of MB left
cmp r4, #0
bne %b35 ; Map next MB
bic r0, r0, #0xF0000000 ; Clear Section Base Address Field
bic r0, r0, #0x0FF00000 ; Clear Section Base Address Field
b %b30 ; Get next element
40 tst r0, #8
bic r0, r0, #0x0C ; clear cachable & bufferable bits in PTE
add r10, r10, #0x0800 ; (r10) = ptr to 1st PTE for "unmapped uncached space"
bne %b25 ; go setup PTEs for uncached space
sub r10, r10, #0x3000 ; (r10) = restore address of 1st level page table
; Setup mmu to map (VA == 0) to (PA == 0x30000000).
ldr r0, =PTs ; PTE entry for VA = 0
ldr r1, =0x3000040E ; uncache/unbuffer/rw, PA base == 0x30000000
str r1, [r0]
; uncached area.
add r0, r0, #0x0800 ; PTE entry for VA = 0x0200.0000 , uncached
ldr r1, =0x30000402 ; uncache/unbuffer/rw, base == 0x30000000
str r1, [r0]
; Comment:
; The following loop is to direct map RAM VA == PA. i.e.
; VA == 0x30XXXXXX => PA == 0x30XXXXXX for S3C2400
; Fill in 8 entries to have a direct mapping for DRAM
;
ldr r10, =PTs ; restore address of 1st level page table
ldr r0, =PHYBASE
add r10, r10, #(0x3000 / 4) ; (r10) = ptr to 1st PTE for 0x30000000
add r0, r0, #0x1E ; 1MB cachable bufferable
orr r0, r0, #0x400 ; set kernel r/w permission
mov r1, #0
mov r3, #64
45 mov r2, r1 ; (r2) = virtual address to map Bank at
cmp r2, #0x20000000:SHR:BANK_SHIFT
add r2, r10, r2, LSL #BANK_SHIFT-18
strlo r0, [r2]
add r0, r0, #0x00100000 ; (r0) = PTE for next physical page
subs r3, r3, #1
add r1, r1, #1
bgt %b45
ldr r10, =PTs ; (r10) = restore address of 1st level page table
; The page tables and exception vectors are setup.
; Initialize the MMU and turn it on.
mov r1, #1
mcr p15, 0, r1, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r10, c2, c0, 0
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mov r1, #0x0071 ; Enable: MMU
orr r1, r1, #0x0004 ; Enable the cache
ldr r0, =VirtualStart
cmp r0, #0 ; make sure no stall on "mov pc,r0" below
mcr p15, 0, r1, c1, c0, 0
mov pc, r0 ; & jump to new virtual address
nop
; MMU & caches now enabled.
; (r10) = physcial address of 1st level page table
;
VirtualStart
mov sp, #0x80000000
add sp, sp, #0x30000 ; arbitrary initial super-page stack pointer
b main
ENTRY_END
LTORG
;------------------------------------------------------------------------------
; Memory Controller Configuration
;
; The below defines are used in the MEMCTRLTAB table
; defined below to iniatialize the memory controller's
; register bank.
;
; SDRAM refresh control register configuration
REFEN EQU (0x1) ; Refresh enable
TREFMD EQU (0x0) ; CBR(CAS before RAS)/Auto refresh
Trp EQU (0x2) ; 2clk
Trc EQU (0x3) ; 7clk
Tchr EQU (0x2) ; 3clk
REFCNT EQU (1113) ; period=15.6us, HCLK=60Mhz, (2048+1-15.6*60)
; Bank Control
;
; Bus width and wait status control
B1_BWSCON EQU (DW32)
B2_BWSCON EQU (DW16)
B3_BWSCON EQU (DW16 + WAIT + UBLB)
B4_BWSCON EQU (DW16)
B5_BWSCON EQU (DW16)
B6_BWSCON EQU (DW32)
B7_BWSCON EQU (DW32)
; Bank 0
B0_Tacs EQU (0x0) ; 0clk
B0_Tcos EQU (0x0) ; 0clk
B0_Tacc EQU (0x7) ; 14clk
B0_Tcoh EQU (0x0) ; 0clk
B0_Tah EQU (0x0) ; 0clk
B0_Tacp EQU (0x0)
B0_PMC EQU (0x0) ; normal
; Bank 1
B1_Tacs EQU (0x0) ; 0clk
B1_Tcos EQU (0x0) ; 0clk
B1_Tacc EQU (0x7) ; 14clk
B1_Tcoh EQU (0x0) ; 0clk
B1_Tah EQU (0x0) ; 0clk
B1_Tacp EQU (0x0)
B1_PMC EQU (0x0) ; normal
; Bank 2
B2_Tacs EQU (0x0) ; 0clk
B2_Tcos EQU (0x0) ; 0clk
B2_Tacc EQU (0x7) ; 14clk
B2_Tcoh EQU (0x0) ; 0clk
B2_Tah EQU (0x0) ; 0clk
B2_Tacp EQU (0x0)
B2_PMC EQU (0x0) ; normal
; Bank 3
B3_Tacs EQU (0x0) ; 0clk
B3_Tcos EQU (0x0) ; 0clk
B3_Tacc EQU (0x7) ; 14clk
B3_Tcoh EQU (0x0) ; 0clk
B3_Tah EQU (0x0) ; 0clk
B3_Tacp EQU (0x0)
B3_PMC EQU (0x0) ; normal
; Bank 4
B4_Tacs EQU (0x0) ; 0clk
B4_Tcos EQU (0x0) ; 0clk
B4_Tacc EQU (0x7) ; 14clk
B4_Tcoh EQU (0x0) ; 0clk
B4_Tah EQU (0x0) ; 0clk
B4_Tacp EQU (0x0)
B4_PMC EQU (0x0) ; normal
; Bank 5
B5_Tacs EQU (0x0) ; 0clk
B5_Tcos EQU (0x0) ; 0clk
B5_Tacc EQU (0x7) ; 14clk
B5_Tcoh EQU (0x0) ; 0clk
B5_Tah EQU (0x0) ; 0clk
B5_Tacp EQU (0x0)
B5_PMC EQU (0x0) ; normal
; Bank 6
B6_MT EQU (0x3) ; SDRAM
B6_Trcd EQU (0x2) ; 4clk
B6_SCAN EQU (0x1) ; 9bit
; Bank 7
;
; Note - there is no memory connected to Bank 7
B7_MT EQU (0x3) ; SDRAM
B7_Trcd EQU (0x2) ; 4clk
B7_SCAN EQU (0x1) ; 9bit
;------------------------------------------------------------------------------
; Memory Controller Configuration Data Table
;
; This data block is loaded into the memory controller's
; registers to configure the platform memory.
;
MEMCTRLTAB DATA
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ; BANKCON0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ; BANKCON1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ; BANKCON2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ; BANKCON3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ; BANKCON4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ; BANKCON5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ; BANKCON6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ; BANKCON7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ; REFRESH
DCD 0xB2 ; BANKSIZE
DCD 0x20 ; MRSRB6
DCD 0x20 ; MRSRB7
END
;-------------------------------------------------------------------------------
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