pxa-dma.h

基于wince5.0的GSPI8686 wifi驱动源代码

/*
File name: pxa-dma.h
Description: This is an extension for DMA registers

*/
#ifndef _PXA_DMA_H
#define _PXA_DMA_H
#if __cplusplus
extern "C" 
{
#endif

#include <windows.h>
#include <nkintr.h>
#include <ceddk.h>
#include <bulverde.h>


#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
#define DDADR_STOP	(1 << 0)		/* Stop (read / write) */

#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */


#define DCSR_RUN		(1 << 31)	/* Run Bit (read / write) */
#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
#define DCSR_EORINT		(1 << 9)		/* End of Receive */
#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
#define DCSR_BUSERR		(1 << 0)	/* Bus Error Interrupt (read / write) */


#define DRCMR_MAPVAL	(0x1U << 7)	/* Map Valid (read/write) */

///Channel Map for SSP
///Ref: Table 5-10 of bulverde development document chapter 5 "DMA Controller"
#define DMA_CHMAP_SSP1_RX	13
#define DMA_CHMAP_SSP1_TX	14

#define DMA_CHMAP_SSP2_RX	15
#define DMA_CHMAP_SSP2_TX	16

#define DMA_CHMAP_SSP3_RX	63 + 963
#define DMA_CHMAP_SSP3_TX	63 + 964


#define	DMA_DCSR(channel)	(BULVERDE_BASE_REG_PA_DMAC+channel*4)


typedef struct _mydmaparam
{
	volatile BULVERDE_DMA_REG		*pDMARegs;	///Base address of DMA registers
	DWORD				channel;				///DMA channel
	HANDLE				dmaWaitObj;
} MYDMAPARAM;


#if __cplusplus
}
#endif ///__cplusplus
#endif ///_PXA_DMA_H