pxa-gspi.c

基于wince5.0的GSPI8686 wifi驱动源代码

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  

pxa-gspi.c

Abstract:  

Holds implementation of pcmcia serial driver interface.  This serial PDD
makes use of the ser16550 library to do most of the work.

Functions:


Notes: 


--*/
#include <windows.h>
#include <nkintr.h>
#include <ndis.h>

#include <types.h>
#include <memory.h>
#include <tchar.h>

#include <ceddk.h>
#include <bulverde.h>

#include <xllp_dmac.h>
#include <Devload.h>

#include <giisr.h>

#include "myintr.h"
#include "pxa-gpio.h"
#include "pxa-ssp.h"
#include "pxa-dma.h"
#include "pxa-gspi.h"
#include "sspioctl.h"

#ifdef DEBUG
#define		GSPIMSG		DEBUGMSG
#else
#define		GSPIMSG		RETAILMSG
#endif ///DEBUG


///int		g_fmDnRdy = FALSE;

extern int		g_spi_dummy_clk_reg;
extern int		g_spi_dummy_clk_data;

///volatile BULVERDE_DMA_REG		*pg_DMARegs;
static LPCTSTR pg_szActiveKey = _T("GSPI8385");

///============================================================================
/// Flags to control the displayed message
#define		ERRMSG		1			///Display the Error Message, only when error occurred
#define		FUNCTAG		0			///Display the message to show the function enter/exit
#define		TICKCNTMSG	0			///Display the Tick count message
#define		PROGFLOW	0			///Display the message to show the program's running flow
#define		TX_FRAG		1			///Display the message whenever the fragmentation is needed in TX
#define		RX_FRAG		1			///Display the message whenever the fragmentation is needed in RX
#define		DMA_MSG		0			///Display the message for debuggin the DMA module
#define		PERF_MSG	1			///Display the message for performance tuning
///============================================================================
#define ENTERFUNC()		GSPIMSG(FUNCTAG,(L"Enter %s\n", TEXT(__FUNCTION__)))
#define EXITFUNC(x)		GSPIMSG(FUNCTAG, (L"Exit %s (%d)\n", TEXT(__FUNCTION__), x))



#define	GSPI_MAX_REG_RETRY		3

static GSPI_STATUS setup_write_dma(PSSP_HARDWARE_CONTEXT pHC, int n);
static GSPI_STATUS setup_read_dma(PSSP_HARDWARE_CONTEXT pHC, int n);
///////////////////////////////////////////////////////////////////////////////
#if (SSPCTRLER == 1)
#define		SSPREG_PHY_BASE		BULVERDE_BASE_REG_PA_SSP1
#define		DMA_CHMAP_SSP_RX	DMA_CHMAP_SSP1_RX
#define		DMA_CHMAP_SSP_TX	DMA_CHMAP_SSP1_TX

#define		XLLP_DMAC_SSP_RX	XLLP_DMAC_SSP_1_RX
#define		XLLP_DMAC_SSP_TX	XLLP_DMAC_SSP_1_TX
#elif (SSPCTRLER == 2)
#define		SSPREG_PHY_BASE		BULVERDE_BASE_REG_PA_SSP2
#define		DMA_CHMAP_SSP_RX	DMA_CHMAP_SSP2_RX
#define		DMA_CHMAP_SSP_TX	DMA_CHMAP_SSP2_TX

#define		XLLP_DMAC_SSP_RX	XLLP_DMAC_SSP_2_RX
#define		XLLP_DMAC_SSP_TX	XLLP_DMAC_SSP_2_TX
#elif (SSPCTRLER == 3)
#define		SSPREG_PHY_BASE		BULVERDE_BASE_REG_PA_SSP3
#define		DMA_CHMAP_SSP_RX	DMA_CHMAP_SSP3_RX
#define		DMA_CHMAP_SSP_TX	DMA_CHMAP_SSP3_TX

#define		XLLP_DMAC_SSP_RX	XLLP_DMAC_SSP_3_RX
#define		XLLP_DMAC_SSP_TX	XLLP_DMAC_SSP_3_TX
#endif ///SSPCTRLER



///---------------------------------------------------------
///Signal Definition
///
#define		SSP_SCLK			23
#define		SSP_SFRM			24
#define		SSP_TX				25
#define		SSP_RX				26
#define		SSP_INTR			22

#define		SSPSCLK_ATTR		GPIO_ALT_FN_2_OUT
#define		SSPSFRM_ATTR		GPIO_OUT
#define		SSPTX_ATTR			GPIO_ALT_FN_2_OUT
#define		SSPRX_ATTR			GPIO_ALT_FN_1_IN
#define		SSPIRQ_ATTR			GPIO_IN


///Define DMA channel
#define		DMA_CH_READ			8
#define		DMA_CH_RW			24

///#define		SSP_IRQNUM			22			///Trial value from sdhc_mainstoneii.reg

#define		MVL_DEF_DRR			0x05
#define		MVL_DEF_DRP			0x0e
///CLK dividend
static int clkdiv = 0;

///---------------------------------------------------------
///Buffer defintion
///
#define PXA_SSP_BLKSZ_MAX				(1<<9)
///crlo: One data packet is about 1514 + wcb => We allocate bigger buffer so that
///			no need to re-enable DMA to accelerate the speed
///#define PXA_SSP_BLOCKS_PER_BUFFER		(3)
#define PXA_SSP_BLOCKS_PER_BUFFER		(6)
#define PXA_SSP_IODATA_SIZE				(PXA_SSP_BLOCKS_PER_BUFFER * \
											PXA_SSP_BLKSZ_MAX)

///---------------------------------------------------------
///DMA ISR functions
///
/// Maximum waiting period (us)
///#define		MAX_WAITus		100000   //dralee 100ms
#define		MAX_WAITus		2000   //crlo 2ms
///#define		MAX_WAITus		10000000   //dralee 100ms

// the dmcd struct is for documentation
struct dcmdRegBits 
{
    unsigned len         :13;
    unsigned rsv0        :1;   
    unsigned width       :2; 
    unsigned size        :2;
    unsigned endian      :1;
    unsigned flybyt      :1;
    unsigned flybys      :1;
    unsigned endirqen    :1;
    unsigned startirqen  :1;
    unsigned rsv1        :5;
    unsigned flowtrg     :1;
    unsigned flowsrc     :1;
    unsigned inctrgadd   :1;
    unsigned incsrcadd   :1;
};

union DMACmdReg// allow bitfields or masks
{
    volatile struct dcmdRegBits DcmdReg ;
    volatile DWORD DcmdDword;
} ;

#define DEFAULT_IST_PRIORITY 101
///#define DEFAULT_IST_PRIORITY 249
///#define SSP_DMA_INTR					(SYSINTR_FIRMWARE+1)
///#define SSP_DMA_INTR					(SYSINTR_FIRMWARE+1)


///static ULONG dma_irqr(PSSP_HARDWARE_CONTEXT	pHC);
///static ULONG dma_irqw(VOID* devid);
static BOOLEAN dma_ist(LPVOID param, DWORD dwSysIntr);
static BOOLEAN dev_ist(PSSP_HARDWARE_CONTEXT pHC, DWORD dwSysIntr);

static GSPI_STATUS ssp_write_data_direct(DWORD hDC, PWORD data, WORD reg, WORD nword);
static GSPI_STATUS ssp_read_data_direct(DWORD hDC, WORD* data, WORD reg, WORD nword, WORD dummy_clk);
///---------------------------------------------------------
//The function was modified from XllpOstDelayMicroSeconds() in XLLP\xllp_ost.c
//
// OST Tick constants
//
#define XLLP_OST_TICKS_MS    3250          // 1ms in ticks (3.25x10^6tick/sec * 1/1000sec/msec)
#define XLLP_OST_TICKS_US    3             // 1usec in ticks (3.25x10^6tick/sec * 1/1000000sec/usec)

static void XllpOstDelayTicks 
     (volatile BULVERDE_OST_REG * pOstRegs, DWORD ticks)
{   
 
	volatile DWORD    expireTime;
	volatile DWORD    time=0;
/*

    DWORD i,j;

    for(j=0;j<ticks;j++)
    {
       for(i=0; i<20; i++ )
           time += ticks;  
    } 
          
    pOstRegs->oscr0 = 0; 
*/   

	time = pOstRegs->oscr0;
	expireTime = time + ticks;

	//
	// Check if we wrapped on the expireTime
	// and delay first part until wrap
	//   
	if (expireTime < time) 
	{
		GSPIMSG(TICKCNTMSG,(L"%s, Timer is wrapped (expt, t)=(%xh, %xh)\n", TEXT(__FUNCTION__), expireTime, time));
		while (time <= pOstRegs->oscr0);

		GSPIMSG(TICKCNTMSG,(L"%s, timer is wrapped (leave)\n", TEXT(__FUNCTION__)));
	}
	///crlo: udelay problem ++
	while (pOstRegs->oscr0 <= expireTime) {
		if ((time<expireTime) && (pOstRegs->oscr0 < time)) {
			///crlo: Get the corner case. If expireTime is approaching (or =) MAX, oscr0 will almost always < expireTime
			///			=> System will be block in here forever
			///[  (oscr0)   ....... (time) ...... (exprieTime)]
			RETAILMSG(1, (L"Get the corner case of Delay, (%d, %d %d)\n", pOstRegs->oscr0, time, expireTime));
			break;
		}
	}
	///Old Implementation
	///while (pOstRegs->oscr0 <= expireTime);
	///crlo: udelay problem -- 

    return;
}

void udelay(volatile BULVERDE_OST_REG *pOstRegs, DWORD ms)
{
	DWORD		ticks;

	ticks = ms * XLLP_OST_TICKS_US * 3;  // approx. 3 ticks per microsecond. 
	XllpOstDelayTicks (pOstRegs, ticks);
	return;
}

///////////////////////////////////////////////////////////////////////////////
/// Core functions of the SSP interface accessing
/// 
static GSPI_STATUS setup_write_dma(PSSP_HARDWARE_CONTEXT pHC, int n)
{
	GSPI_STATUS		result = GSPI_SUCCESS;
	volatile DMADescriptorChannelType *desc = pHC->write_desc;
	MYDMAPARAM		*pDmaParam = &pHC->DMAParam[WTDMA_PARAM];

	desc->ddadr |= DDADR_STOP;
	desc->dcmd &= ~(DCMD_LENGTH);

	desc->dcmd |= n;
	
	if (n > PXA_SSP_IODATA_SIZE) {
		GSPIMSG(ERRMSG|PERF_MSG, (TEXT("Requested length is too large (limit, req) = (%d, %xh)\n"), PXA_SSP_IODATA_SIZE, n));
	}

	///Start DMA channel
	pHC->pDMARegs->ddg[pDmaParam->channel].ddadr = (UINT32) pHC->write_desc_phys_addr;
	pHC->pDMARegs->dcsr[pDmaParam->channel] |=  DCSR_RUN;		/// set the RUN bit

	///Wait here until it's done
	///crlo:dmawait ++
	{
	int		i;
	for (i=0 ; i<MAX_WAITus ; i++) {
		volatile DWORD		dcsr = pHC->pDMARegs->dcsr[pDmaParam->channel];

		if (dcsr & DCSR_STOPSTATE) {
			break;
		}
		udelay(pHC->pOSTRegs, 1);
	}
	if (i == MAX_WAITus) {
		GSPIMSG(ERRMSG, (TEXT("Wt-DMA timeout (%d), lp: %d\n"), n, i));
	}
	///=> We found if no delay, even in accessing the short data (eg: register)
	///	it's possible the data can not be written successfully
	///if (n > 4) {
		///We are reading the data, not registers
		udelay(pHC->pOSTRegs, 5);			///Trial value
	///}
	}

	///crlo:dmawait --

	/*
	///
	///crlo-2k60704: Old implementation
	///Wait here until it's done
	{
		int		lp;
		volatile DWORD	dcsr;
		for (lp=0 ; lp<MAX_WAITus ; lp++) {			///Trial period (1s)
			dcsr = pHC->pDMARegs->dcsr[pDmaParam->channel];
			if (dcsr & (DCSR_STOPSTATE)) {
				///GSPIMSG(1, (TEXT("wt(%d) (lp,dcsr) = (%d, %xh)\n"), n, lp, dcsr));
				break;
			}
			udelay(pHC->pOSTRegs, 1);
			///NdisMSleep(1);
			///for (a=0 ; a<10 ; a++) ;
		}
		if (lp == MAX_WAITus) {
			GSPIMSG(ERRMSG, (TEXT("Wt-DMA(%d) (lp, dcsr) = (%d, %xh)\n"), n, lp, dcsr));
			result = GSPI_TIMEOUT;
		///} else {
			///GSPIMSG(1, (TEXT("Wt-DMA ok, dcsr= %xh\n"), dcsr));
		}
		///Add one more delay at the end. Otherwise, the firmware download will failed. 
		/// (Don't know why)
		udelay(pHC->pOSTRegs, 50);			///Trial value
		///NdisMSleep(1);
	}
	*/
///funcFinal:
	return result;
}

static GSPI_STATUS ssp_write_data_direct(DWORD hDC, PWORD data, WORD reg, WORD nword)
{
	int		result = GSPI_SUCCESS;
	PSSP_HARDWARE_CONTEXT	pHC;
	int		nbyte;
	///crlo:length-fix ++
	int		fragnbyte, accnbyte;
	BOOLEAN	 needToWriteReg = TRUE;
	BOOLEAN		isFrag = FALSE;
	///crlo:length-fix --

	///GSPIMSG(1, (TEXT("w(%d)\n"), (nword*2)));
	ENTERFUNC();
	if (hDC == 0) {
		result = GSPI_INVALIDARGS;
		goto funcLeave;
	}
	pHC = (PSSP_HARDWARE_CONTEXT)hDC;
	EnterCriticalSection(&pHC->SSPCrit);

	///n is a unit of WORD. Convert it to unit of BYTE
	///nbyte = nword * 2;
	nbyte = nword << 1;
	reg |= 0x8000;

	
	set_GPIO_signal(pHC->pGPIORegs, SSP_SFRM,SIG_DOWN);	
	accnbyte = 0;
	///crlo: We write the register address at the beginning
	pHC->pSSPRegs->base.ssdr = reg;

	///crlo: Writing the data 
	while (1) {
		if ((nbyte - accnbyte) > (PXA_SSP_IODATA_SIZE)) {
			fragnbyte = PXA_SSP_IODATA_SIZE;
			GSPIMSG(TX_FRAG|PERF_MSG, (TEXT("Fragment Tx Data (now, exp)=(%d, %d)\n"), (nbyte - accnbyte), nbyte));
			isFrag = TRUE;
		} else {
			fragnbyte = nbyte - accnbyte;
		}
		memcpy(pHC->iodata, data, fragnbyte);

		///DMA mode
		result = setup_write_dma(pHC, fragnbyte);

		if (result != GSPI_SUCCESS) {
			GSPIMSG(ERRMSG, (TEXT("Not successful after sending %d bytes.\n"), accnbyte));
			break;
		}
		
		data += (fragnbyte/2);			///type of Data is WORD
		accnbyte += fragnbyte;
		if (accnbyte == nbyte) {
			if (isFrag == TRUE) {
				GSPIMSG(TX_FRAG|PERF_MSG, (TEXT("Sending %d bytes complete\n"), accnbyte));
			}
			break;