s3c-spi.c

基于wince5.0的GSPI8686 wifi驱动源代码

            L"Failed  p_s3c_wlan_isr_init \r\n" ));
        goto error;				
	}

	InitializeCriticalSection(&(pDeviceContext->cs));

	/*
	* configure pins for spi and intr
	*/
	pDeviceContext->gpio->GPECON &= ~((0x03 << 22) | (0x03 << 24) | (0x03 << 26));  // clear
	pDeviceContext->gpio->GPECON |= (0x02 << 22) | (0x02 << 24) | (0x02 << 26);   // set
	pDeviceContext->gpio->GPEUP |= (0x01 << 11) | (0x01 << 12) | (0x1<<13);
    
	// to config spi_cs as general io pin
	pDeviceContext->gpio->GPGCON &= ~(0x03 << 4);  // clear 
	pDeviceContext->gpio->GPGCON |= 0x01 << 4;   // set
	pDeviceContext->gpio->GPGUP |= (0x01 << 2);


   // Configure the interrupt pin
   pDeviceContext->gpio->GPGCON &= ~(3<<6);
   pDeviceContext->gpio->GPGCON |= (2<<6);
   pDeviceContext->gpio->GPGUP  |= (1<<3);
	pDeviceContext->gpio->EXTINT1 &= ~(0xf<<12);
	pDeviceContext->gpio->EXTINT1 |= (0x2<<12);

	//
	pDeviceContext->spi->SPPRE0  = 1;
	pDeviceContext->spi->SPPIN0 = 0x0; //KEEP=0, SPICS=0,ENMUL=0
	
	{
		WORD	regval;
#if defined (GSPI8385)
			const WORD	chipid = 0x0004;
#elif defined (GSPI8686)
			const WORD	chipid = 0x000b;
#else
			const WORD	chipid = 0x000;
#endif ///GSPI$(CHIPID)
			///ssp_read_register((DWORD)pHC, &regval, 0x00);
			///GSPIMSG(1, (TEXT("Reg(0x00)= 0x%04x\r\n"), regval));
			s3c_spi_read_register(hDevice, 0x02, &regval);
			RETAILMSG(1, (TEXT("Reg(0x02)= 0x%04x\r\n"), regval));
	}
		
	/*
     * And we're done.
     */
     *phDevice = hDevice;

		return TRUE;
		
error:

	s3c_spi_deinit( hDevice);

	*phDevice = NULL;
	return FALSE;
}


void s3c_spi_deinit(SPI_DEVICE_HANDLE hDevice)
{
	SPI_DEVICE_CONTEXT *pDeviceContext = SPIHANDLE_TO_DEVICE(hDevice);
	DWORD irq;

	if(pDeviceContext->thread_wlan != NULL)
	{
		pDeviceContext->exit_isr_wlan = TRUE;

		if(pDeviceContext->event_wlan)
		{
			SetEvent(pDeviceContext->event_wlan);
		}

		WaitForSingleObject(pDeviceContext->event_wlan_exit, INFINITE);

		CloseHandle(pDeviceContext->event_wlan_exit);
       CloseHandle(pDeviceContext->thread_wlan);
  		pDeviceContext->event_wlan_exit = NULL;

	}
	
	if(pDeviceContext->sysintr_wlan != SYSINTR_UNDEFINED)
	{
		irq = IRQ_WLAN;
		
		InterruptDisable(pDeviceContext->sysintr_wlan);

		 if (!KernelIoControl(IOCTL_HAL_RELEASE_SYSINTR, &irq, sizeof(UINT32), &(pDeviceContext->sysintr_wlan), sizeof(UINT32), NULL))
	    {
			RETAILMSG(1, (L"ERROR: p_s3c_isr_init: "
	            L"Failed  release sysintr for wlan \r\n" ));
	    }

		if(pDeviceContext->event_wlan)
		{
			CloseHandle(pDeviceContext->event_wlan);
			pDeviceContext->event_wlan = NULL;
		}	
	}

	DeleteCriticalSection(&(pDeviceContext->cs));

	p_s3c_unmap_register( hDevice);

	LocalFree(pDeviceContext);

}


BOOL s3c_spi_register_isr(SPI_DEVICE_HANDLE hDevice, void *adapter, fnIsrCallBack fnIsr)
{
	SPI_DEVICE_CONTEXT *pDeviceContext = SPIHANDLE_TO_DEVICE(hDevice);

	if((hDevice == NULL) || (adapter == NULL) || (fnIsr == NULL))
		return FALSE;

	pDeviceContext->isrContext = (HANDLE)adapter;
	pDeviceContext->IsrCallBack = fnIsr;

	return TRUE;
}

BOOL s3c_spi_read_register(SPI_DEVICE_HANDLE hDevice, unsigned short RegAdd, unsigned short *pRegData)
{
	SPI_DEVICE_CONTEXT *pDeviceContext = SPIHANDLE_TO_DEVICE(hDevice);
	unsigned short dummy_data = 0xFFFF;
	int i;
	
	//lock spi operation
	EnterCriticalSection(&(pDeviceContext->cs));

	//enable clock
	pDeviceContext->clkpwr->CLKCON |= CLKCON_SPI;

	//configure spi register
	pDeviceContext->spi->SPCON0 = (0x0<<5) | 0x18; //TAGD=0,CPHA=0,CPOL=0,MSTR=1,ENSCK=1, SMOD=polling

	
    // enable cs
   pDeviceContext->gpio->GPGDAT &= ~(0x1 << 2);

	/*
	* write short reg address
	*/
	p_s3c_spi_write_short(hDevice, RegAdd);

	
	/*
	* write dummy clock before read register
	*/
	for(i=0;i<g_spi_dummy_clk_reg;i++)
	{
		p_s3c_spi_write_short(hDevice, dummy_data);
	}

	/*
	* Read data 
	*/
	p_s3c_spi_read_short(hDevice, pRegData);
	 
    // disable cspi
    pDeviceContext->gpio->GPGDAT |= (0x1 << 2);  

	//disable clock
	pDeviceContext->clkpwr->CLKCON &= ~CLKCON_SPI;
	
	//lock spi operation
	LeaveCriticalSection(&(pDeviceContext->cs));

	return TRUE;
	
}


BOOL s3c_spi_write_register(SPI_DEVICE_HANDLE hDevice, unsigned short RegAdd, unsigned short RegData)
{
	SPI_DEVICE_CONTEXT *pDeviceContext = SPIHANDLE_TO_DEVICE(hDevice);
	
	//lock spi operation
	EnterCriticalSection(&(pDeviceContext->cs));

	//enable clock
	pDeviceContext->clkpwr->CLKCON |= CLKCON_SPI;

	//configure spi register
	pDeviceContext->spi->SPCON0 = (0x0<<5) | 0x18; //TAGD=0,CPHA=0,CPOL=0,MSTR=1,ENSCK=1, SMOD=polling
	
    // enable cs
   pDeviceContext->gpio->GPGDAT &= ~(0x1 << 2);

	/*
	* write short reg address NOTE:: | 0x8000 it is write operation
	*/
	p_s3c_spi_write_short(hDevice, (RegAdd | 0x8000));


	/*
	* Write data 
	*/
	p_s3c_spi_write_short(hDevice, RegData);

	 
    // disable cspi
    pDeviceContext->gpio->GPGDAT |= (0x1 << 2);  

	//disable clock
	pDeviceContext->clkpwr->CLKCON &= ~CLKCON_SPI;
	
	//lock spi operation
	LeaveCriticalSection(&(pDeviceContext->cs));

	return TRUE;	
}

BOOL s3c_spi_read_data(SPI_DEVICE_HANDLE hDevice, unsigned short RegAdd, unsigned short *pRegData, unsigned short count)
{
	SPI_DEVICE_CONTEXT *pDeviceContext = SPIHANDLE_TO_DEVICE(hDevice);
	unsigned short dummy_data = 0xFFFF;
	int i;
	
	//lock spi operation
	EnterCriticalSection(&(pDeviceContext->cs));

	//enable clock
	pDeviceContext->clkpwr->CLKCON |= CLKCON_SPI;

	//configure spi register
	pDeviceContext->spi->SPCON0 = (0x0<<5) | 0x18; //TAGD=0,CPHA=0,CPOL=0,MSTR=1,ENSCK=1, SMOD=polling
	
    // enable cs
   pDeviceContext->gpio->GPGDAT &= ~(0x1 << 2);

	/*
	* write short reg address
	*/
	p_s3c_spi_write_short(hDevice, RegAdd);


	/*
	* write dummy clock before read data
	*/
	for(i=0;i<g_spi_dummy_clk_data;i++)
	{
		p_s3c_spi_write_short(hDevice, dummy_data);
	}

	
	/*
	* Read data 
	*/
	for(i=0;i<count;i++)
	{
		p_s3c_spi_read_short(hDevice, pRegData++);
	}

    // disable cspi
    pDeviceContext->gpio->GPGDAT |= (0x1 << 2);  

	//disable clock
	pDeviceContext->clkpwr->CLKCON &= ~CLKCON_SPI;
	
	//lock spi operation
	LeaveCriticalSection(&(pDeviceContext->cs));

	return TRUE;
	
}

BOOL s3c_spi_write_data(SPI_DEVICE_HANDLE hDevice, unsigned short RegAdd, unsigned short *pRegData ,unsigned short count)
{
	SPI_DEVICE_CONTEXT *pDeviceContext = SPIHANDLE_TO_DEVICE(hDevice);
	int i;
	
	//lock spi operation
	EnterCriticalSection(&(pDeviceContext->cs));

	//enable clock
	pDeviceContext->clkpwr->CLKCON |= CLKCON_SPI;

	//configure spi register
	pDeviceContext->spi->SPCON0 = (0x0<<5) | 0x18; //TAGD=0,CPHA=0,CPOL=0,MSTR=1,ENSCK=1, SMOD=polling
	
   // enable cs
   pDeviceContext->gpio->GPGDAT &= ~(0x1 << 2);

	/*
	* write short reg address NOTE:: | 0x8000 it is write operation
	*/
	p_s3c_spi_write_short(hDevice, (RegAdd | 0x8000));


	/*
	* Write data 
	*/
	for(i=0;i<count;i++)
	{
		p_s3c_spi_write_short(hDevice, *pRegData++);
	}
	 
    // disable cspi
    pDeviceContext->gpio->GPGDAT |= (0x1 << 2);  

	//disable clock
	pDeviceContext->clkpwr->CLKCON &= ~CLKCON_SPI;
	
	//lock spi operation
	LeaveCriticalSection(&(pDeviceContext->cs));

	return TRUE;	
}