📄 clear.lst
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C:\TOOLS\CC411\C2000\CGTOOLS\BIN\DSPA.EXE CLEAR.ASM -V2XX -L -X -o CLEAR.OBJ
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Wed Apr 17 14:45:56 2002
Copyright (c) 1987-1999 Texas Instruments Incorporated
CLEAR.ASM PAGE 1
1 **************************************************************************
2 ** PERFORMS THE FOLLOWING: **
3 * **
4 * **
5 * PROGRAM EACH WORD IN ARRAY (NOROWRED) **
6 * | **
7 * | **
8 * PROGRAM EACH WORD (32 TOTAL) IN REDUNDANCY ROWS **
9 * | **
10 * | **
11 * END **
12 * **
13 * NOTES: -PERFORMS PROGRAM VERIFY AFTER EACH **
14 * PROGRAM PULSE IS APPLIED **
15 * **
16 * **
17 **************************************************************************
18 ; Revision history:
19 ;
20 ; 4/12/02: Commented out the line which wrote to the SCSR1 to set up the
21 ; PLL. The PLL is set up in the boot ROM code, and there is
22 ; a selection mechanism to select x2 or x4 mode for the PLL.
23 ; This over-wrote that selection causing the programmer to fail
24 ; when the x2 option was selected, since only the pll register
25 ; got changed, while the baud rate register in the SCI remained
26 ; the same.
27 ;
28
29
30
31 .include ..\include\svar.h
32
33 0000 .text
34
35 0000 START
36
37 0000 bce0 LDP #0E0h
38
39 ;;; SPLK #0060h,7018h -- removed to fix bug 4/12/02
40
41 0001 ae19 SPLK #000bh,7019h
0002 000b
42 0003 ae29 SPLK #6fh,7029h
0004 006f
43
44
45
46
47 0005 bc00 LDP #0
48
49 0006 ae68 SPLK #1000h,FL_SECST ;FIRST ADDRESS OF FLASH SEGMENT
0007 1000
50 0008 ae69 SPLK #1FFFh,FL_SECEND ;LAST ADDRESS IN FLASH SEGMENT
0009 1fff
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Wed Apr 17 14:45:56 2002
Copyright (c) 1987-1999 Texas Instruments Incorporated
CLEAR.ASM PAGE 2
51 000a ae70 SPLK #000fh,SECTOR ;SECTOR KEY
000b 000f
52 000c 7a80 CALL CLEAR ;CLEAR SECTOR 1
000d 0020'
53
54 000e ae68 SPLK #0000h,FL_SECST ;FIRST ADDRESS OF FLASH SEGMENT
000f 0000
55 0010 ae69 SPLK #0FFFh,FL_SECEND ;LAST ADDRESS IN FLASH SEGMENT
0011 0fff
56 0012 ae70 SPLK #000fh,SECTOR ;SECTOR KEY
0013 000f
57 0014 7a80 CALL CLEAR ;CLEAR SECTOR 1
0015 0020'
58
59 0016 bc00- LDPK #ERROR_FLAG
60 0017 ae1f- SPLK #0,ERROR_FLAG
0018 0000
61 0019 ef00 RET
62
63 001a bc06 err1 LDP #6
64 001b ae1f- SPLK #1,ERROR_FLAG
001c 0001
65 001d be32 POP
66 001e be32 POP
67 001f ef00 RET
68 0020 OLIVIER:
69
70
71 ****************************************************************************************
72 .COPY "CLR_ALG.ASM" ;CLEAR ROUTINE
B 1 ********************************************************************************
B 2 ** PERFORMS THE FOLLOWING: **
B 3 * **
B 4 * **
B 5 * PROGRAM EACH WORD IN ARRAY (NOROWRED) **
B 6 * | **
B 7 * | **
B 8 * PROGRAM EACH WORD (32 TOTAL) IN REDUNDANCY ROWS **
B 9 * | **
B 10 * | **
B 11 * END **
B 12 * **
B 13 * NOTES: -PERFORMS PROGRAM VERIFY AFTER EACH **
B 14 * PROGRAM PULSE IS APPLIED **
B 15 * **
B 16 * **
B 17 ********************************************************************************
B 18
B 19 .include ..\include\var.h ;Variable References.
B 20
B 21
B 22
B 23 0000 .SECT "UTILS"
B 24 ********************************************************************************
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Wed Apr 17 14:45:56 2002
Copyright (c) 1987-1999 Texas Instruments Incorporated
CLEAR.ASM PAGE 3
B 25 * FILENAME: PRCLR.asm *
B 26 * FILETYPE: TMS320C2Xlp Assembly Language (Texas Instruments) *
B 27 * *
B 28 * Date: 10/99 *
B 29 ********************************************************************************
B 31 ********************************************************************************
B 32 * PUBLIC DECLERATIONS *
B 33 ********************************************************************************
B 34 *********LABELS********
B 35 .DEF READWORD,CLRCMD,PROG
B 36 .DEF CLR,ERROR1,CLEAR,PPW,NEXTWORD,COMPARE,PGCNT
B 37 *********DELAYS********
B 38 *
B 39 ********************************************************************************
B 40 * FLASH PRECONDITION ERASE ROUTINE (ARRAY - Program Space) *
B 41 ********************************************************************************
B 42 *
B 43 0020 .TEXT
B 44 ********************************************************************************
B 45 ** THE FOLLOWING VARIABLES CAN BE CHANGED IF THERE IS A SPEC CHANGE. **
B 46 ** THE FL_SEGST,FL_SEGEND,ARRAY AND SECTOR VARIABLES DETERMINE WHICH **
B 47 ** ARRAY AND SECTOR IS BEING WORKED ON. **
B 48 ** **
B 49 ********************************************************************************
B 50 ********************************************************************************
B 51 ; Define macros to set the Flash Mode.
B 52 ; ACCESS_REGS gives access to the Flash Registers in the Pgm Mem Space
B 53 ; and ACCESS_ARRAY gives access to the Flash ARRAY in Pgm Mem Space.
B 54 ;
B 55 ********************************************************************************
B 56 ACCESS_REGS .macro
B 57 OUT 07fh,0ff0fh
B 58 .endm
B 59
B 60 ACCESS_ARRAY .macro
B 61 IN 07fh,0ff0fh
B 62 .endm
B 63
B 64 ********************************************************************************
B 65 ; Define Short DELAY loop macro.
B 66 ; This will be used to generate a short delay upto 256 cycles.
B 67 ********************************************************************************
B 68 SDELAY .macro COUNT
B 69 RPT COUNT
B 70 NOP
B 71 .endm
B 72 ********************************************************************************
B 73 ** THE FOLLOWING PROGRAM WILL PRECONDITION A SECTOR **
B 74 ** - CALLED BY CLRx.ASM, WHICH DETERMINES WHICH ARRAY AND SECTOR **
B 75 ** WILL BE PROGRAMMED **
B 76 ********************************************************************************
B 77
B 78 0020 bc00 CLEAR LDP #0 ;DP => 0
B 79
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Wed Apr 17 14:45:56 2002
Copyright (c) 1987-1999 Texas Instruments Incorporated
F10 'LF240x FLASH MEMORY PRECONDITION ROUTINE PAGE 4
B 80
B 81
B 82
B 83 ********************************************************************************
B 84 ** SUBROUTINE: ENABL **
B 85 ** - PLACE FLASH IN REGISTER MODE **
B 86 ** - ENABLES SECTOR **
B 87 ** - WRITES A ONE TO THE APPROPRIATE "ENABLE" REG **
B 88 ** **
B 89 ********************************************************************************
B 90 0021 ENABL ACCESS_REGS
1B 0021 0c7f OUT 07fh,0ff0fh
0022 ff0f
B 91
B 92 0023 bf80 LACC #SECT ;ENABLE SECTOR
0024 0006
B 93 0025 a861 BLDD #SECTOR,PAD
0026 0070
B 94 0027 a761 TBLW PAD
B 95
B 96 0028 bf80 LACC #ENAB ;ENABLE CORE
0029 0005
B 97 002a ae61 SPLK #0001h,PAD
002b 0001
B 98 002c a761 TBLW PAD
B 99
B 100 ********************************************************************************
B 101 ** MAINBODY: **
B 102 ** - DATA -> 0000 FOR USE IN COMPARE **
B 103 ** - INITIALIZES AR4 (OPTIONAL PULSE COUNT) **
B 104 ** - CALLS CLR WITH ROW REDUNDANCY DISABLED **
B 105 ** - PREVENTS BITS THAT ARE MAPPED OUT BY RED FROM GOING **
B 106 ** INTO DEPLETION DURING ERASE **
B 107 ** - CALLS CLR WITH PRECONDITIONING **
B 108 ** - PREVENTS BITS IN UNUSED REDROW FROM GOING INTO **
B 109 ** DEPLETION DUREING ERASE **
B 110 ********************************************************************************
B 111 002d ae64 SPLK #0000h,DATA ;LOAD 0000 FOR COMPARE
002e 0000
B 112 002f b400 LAR AR4,#0h ;INITIALIZE PULSE COUNT (OPTIONAL)
B 113
B 114 0030 ae6a SPLK #0080h,FL_CMD ;NOROWRED
0031 0080
B 115 0032 7a80 CALL CLR ;CLEAR MAIN ARRAY (NOROWRED)
0033 003b'
B 116
B 117 0034 ae6a SPLK #0100h,FL_CMD ;SETUP ENABLE REDUNDANCY,ENABLE PRECOND
0035 0100
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