system_stm32.c

Cortex-m3微控制器软件接口标准 不错的资料

   #error "PLLSRC: PLL entry clock source (RCC_CFGR.16) wrong"
#endif

#if (CHECK_RANGE((__CSSON_), 0, 1))
   #error "CSSON: Clock Security System enable (RCC_CR.19) wrong"
#endif

#if (CHECK_RANGE((__HSEBYP_), 0, 1))
   #error "HSEBYP: External High Speed clock Bypass (RCC_CR.18) wrong"
#endif

#if (CHECK_RANGE((__HSEON_), 0, 1))
   #error "HSEON: External High Speed clock enable (RCC_CR.16) wrong"
#endif

#if (CHECK_RANGE((__HSITRIM_), 0, 31))
   #error "HSITRIM: Internal High Speed clock trimming (RCC_CR.3..7) wrong"
#endif

#if (CHECK_RANGE((__HSION_), 0, 1))
   #error "HSION: Internal High Speed clock enable (RCC_CR.0) wrong"
#endif

#if (((__MCO_) != 0) && (((__MCO_) < 4) || ((__MCO_) > 7)))
   #error "MCO: Microcontroller Clock Output (RCC_CFGR.24..26) wrong"
#endif

#if (CHECK_RANGE((__USBPRE_), 0, 1))
   #error "USBPRE: USB prescaler (RCC_CFGR.22) wrong"
#endif

#if (CHECK_RANGE((__ADCPRE_), 0, 3))
   #error "ADCPRE: ADC prescaler (RCC_CFGR.14..15) wrong"
#endif

#if (((__PPRE2_) != 0) && (((__PPRE2_) < 4) || ((__PPRE2_) > 7)))
   #error "PPRE2: APB High speed prescaler (APB2) (RCC_CFGR.11..13) wrong"
#endif

#if (((__PPRE1_) != 0) && (((__PPRE1_) < 4) || ((__PPRE1_) > 7)))
   #error "PPRE1: APB Low speed prescaler (APB1) (RCC_CFGR.8..10) wrong"
#endif

#if (((__HPRE_) != 0) && (((__HPRE_) < 8) || ((__HPRE_) > 15)))
   #error "HPRE: AHB prescaler (RCC_CFGR.4..7) wrong"
#endif

#if (CHECK_RANGE((__SW_), 0, 2))
   #error "SW: System Clock Switch (RCC_CFGR.0..1) wrong"
#endif

#if (((__HSE) < 4000000) || ((__HSE) > 16000000))
   #error "HSE: External High Speed Clock wrong"
#endif


/*----------------------------------------------------------------------------
  Compute the register values
 *----------------------------------------------------------------------------*/
#define __RCC_CR_VAL    (  \
      (( __PLLON_)    << 24)  \
    | (( __CSSON_)    << 19)  \
    | (( __HSEBYP_)   << 18)  \
    | (( __HSEON_)    << 16)  \
    | (( __HSITRIM_)  <<  3)  \
    | (( __HSION_)    <<  0)  \
                        )

#define __RCC_CFGR_VAL  (  \
      (( __MCO_)      << 24)  \
    | (( __USBPRE_)   << 22)  \
    | (( __PLLMUL_)   << 18)  \
    | (( __PLLXTPRE_) << 17)  \
    | (( __PLLSRC_)   << 16)  \
    | (( __ADCPRE_)   << 14)  \
    | (( __PPRE2_)    << 11)  \
    | (( __PPRE1_)    <<  8)  \
    | (( __HPRE_)     <<  4)  \
    | (( __SW_)       <<  0)  \
                        )

#define __EFI_ACR_Val   (  \
      (( __PRFTBS_)   <<  5)  \
    | (( __PRFTBE_)   <<  4)  \
    | (( __HLFCYA_)   <<  3)  \
    | (( __LATENCY_)  <<  0)  \
                        )


/*----------------------------------------------------------------------------
  RCC Defines
 *----------------------------------------------------------------------------*/
/* register RCC_CR -----------------------------------------------------------*/
#define RCC_CR_HSION       (0x00000001)              /* Internal High Speed clock enable     */
#define RCC_CR_HSIRDY      (0x00000002)              /* Internal High Speed clock ready flag */
#define RCC_CR_HSEON       (0x00010000)              /* External High Speed clock enable     */
#define RCC_CR_HSERDY      (0x00020000)              /* External High Speed clock ready flag */
#define RCC_CR_PLLON       (0x01000000)              /* PLL enable                           */
#define RCC_CR_PLLRDY      (0x02000000)              /* PLL clock ready flag                 */

/* register RCC_CFGR ---------------------------------------------------------*/
#define RCC_CFGR_SW        (0x00000003)              /* System clock Switch                  */
#define RCC_CFGR_SWS       (0x0000000C)              /* System Clock Switch Status           */
#define RCC_CFGR_HPRE      (0x000000F0)              /* AHB prescaler                        */
#define RCC_CFGR_PRE1      (0x00000700)              /* APB Low speed prescaler (APB1)       */    
#define RCC_CFGR_PRE2      (0x00003800)              /* APB High speed prescaler (APB2)      */ 
#define RCC_CFGR_PLLSRC    (0x00010000)              /* PLL entry clock source               */
#define RCC_CFGR_PLLXTPRE  (0x00020000)              /* HSE divider for PLL entry            */
#define RCC_CFGR_PLLMULL   (0x003C0000)              /* PLL Multiplication Factor            */


/*----------------------------------------------------------------------------
  DEFINES
 *----------------------------------------------------------------------------*/


    
/*----------------------------------------------------------------------------
  Define SYSCLK
 *----------------------------------------------------------------------------*/
#define __HSI (8000000UL)

#define __PLLMULL (((__RCC_CFGR_VAL & RCC_CFGR_PLLMULL) >> 18) + 2)

#if   ((__RCC_CFGR_VAL & RCC_CFGR_SW) == 0x00) 
  #define __SYSCLK   __HSI                           /* HSI is used as system clock */
#elif ((__RCC_CFGR_VAL & RCC_CFGR_SW) == 0x01)
  #define __SYSCLK   __HSE                           /* HSE is used as system clock */
#elif ((__RCC_CFGR_VAL & RCC_CFGR_SW) == 0x02)
  #if (__RCC_CFGR_VAL & RCC_CFGR_PLLSRC)             /* HSE is PLL clock source     */
    #if (__RCC_CFGR_VAL & RCC_CFGR_PLLXTPRE)         /* HSE/2 is used               */
      #define __SYSCLK  ((__HSE >> 1) * __PLLMULL)   /* SYSCLK = HSE/2 * pllmull    */
    #else                                            /* HSE is used                 */
      #define __SYSCLK  ((__HSE >> 0) * __PLLMULL)   /* SYSCLK = HSE   * pllmul     */
    #endif  
  #else                                              /* HSI/2 is PLL clock source   */
    #define __SYSCLK  ((__HSI >> 1) * __PLLMULL)     /* SYSCLK = HSI/2 * pllmul     */
  #endif
#else
   #error "ask for help"
#endif
   
/*----------------------------------------------------------------------------
  Define  AHBCLK
 *----------------------------------------------------------------------------*/
#define __AHBCLKPRESC  ((__RCC_CFGR_VAL & RCC_CFGR_HPRE) >> 4)

#if (__AHBCLKPRESC & 0x08)
  #define __AHBCLK        (__SYSCLK >> ((__AHBCLKPRESC & 0x07)+1))
#else
  #define __AHBCLK        (__SYSCLK)
#endif

/*----------------------------------------------------------------------------
  Define  APB1CLK
 *----------------------------------------------------------------------------*/
#define __APB1CLKPRESC  ((__RCC_CFGR_VAL & RCC_CFGR_PRE1) >> 8)

#if (__APB1CLKPRESC & 0x04)
  #define __APB1CLK       (__AHBCLK >> ((__APB1CLKPRESC & 0x03)+1))
#else
  #define __APB1CLK       (__AHBCLK)
#endif

/*----------------------------------------------------------------------------
  Define  APB2CLK
 *----------------------------------------------------------------------------*/
#define __APB2CLKPRESC  ((__RCC_CFGR_VAL & RCC_CFGR_PRE2) >> 11)

#if (__APB2CLKPRESC & 0x04)
  #define __APB2CLK       (__AHBCLK >> ((__APB2CLKPRESC & 0x03)+1))
#else
  #define __APB2CLK       (__AHBCLK)
#endif


/*----------------------------------------------------------------------------
  Const Definitions
 *----------------------------------------------------------------------------*/
const uint32_t SystemFrequency         = __AHBCLK;   /*!< System Clock Frequency (Core Clock) */
const uint32_t SystemFrequency_SysClk  = __SYSCLK;   /*!< System clock                        */
const uint32_t SystemFrequency_AHBClk  = __AHBCLK;   /*!< AHB System bus speed                */
const uint32_t SystemFrequency_APB1Clk = __APB1CLK;  /*!< APB Peripheral bus 1 (low)  speed   */
const uint32_t SystemFrequency_APB2Clk = __APB2CLK;  /*!< APB Peripheral bus 2 (high) speed   */


/**
 * Initialize the system
 *
 * @param  none
 * @return none
 *
 * @brief  Setup the microcontroller system
 *         Initialize the Embedded Flash Interface,  initialize the PLL and update th SystemFrequency variable
 */
void SystemInit (void)
{
  FLASH->ACR = __EFI_ACR_Val;                        /* set access control register        */

  RCC->CFGR = __RCC_CFGR_VAL;                        /* set clock configuration register   */
  RCC->CR   = __RCC_CR_VAL;                          /* set clock control register         */

  if (__RCC_CR_VAL & RCC_CR_HSION) {                 /* if HSI enabled                     */
    while ((RCC->CR & RCC_CR_HSIRDY) == 0);          /* Wait for HSIRDY = 1 (HSI is ready) */
  }

  if (__RCC_CR_VAL & RCC_CR_HSEON) {                 /* if HSE enabled                     */
    while ((RCC->CR & RCC_CR_HSERDY) == 0);          /* Wait for HSERDY = 1 (HSE is ready) */
  }

  if (__RCC_CR_VAL & RCC_CR_PLLON) {                 /* if PLL enabled                     */
    while ((RCC->CR & RCC_CR_PLLRDY) == 0);          /* Wait for PLLRDY = 1 (PLL is ready) */
  }

  /* Wait till SYSCLK is stabilized (depending on selected clock) */
  while ((RCC->CFGR & RCC_CFGR_SWS) != ((__RCC_CFGR_VAL<<2) & RCC_CFGR_SWS));
}