system_stm32.c

Cortex-m3微控制器软件接口标准 不错的资料

/******************************************************************************
 * @file:    system_stm32.c
 * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File
 * @version: V1.0
 * @date:    12. Nov. 2008
 *----------------------------------------------------------------------------
 *
 * Copyright (C) 2008 ARM Limited. All rights reserved.
 *
 * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
 * processor based microcontrollers.  This file can be freely distributed 
 * within development tools that are supporting such ARM based processors. 
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/


#include <stdint.h>
#include "stm32.h"


//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//

// <h> Embedded Flash Configuration
//   <h> Flash Access Control Configuration (FLASH_ACR)
//     <o.0..2> LATENCY: Latency (FLASH_ACR.0..2)
//       <i> Default: 2 wait states
//                     <0=> 0 wait states
//                     <1=> 1 wait states
//                     <2=> 2 wait states
#define __LATENCY_ 2

//     <o.0> HLFCYA: Flash Half Cycle Access Enable (FLASH_ACR.3)
#define __HLFCYA_ 0

//     <o.0> PRFTBE: Prefetch Buffer Enable (FLASH_ACR.4)
#define __PRFTBE_ 1

//     <o.0> PRFTBS: Prefetch Buffer Status Enable (FLASH_ACR.5)
#define __PRFTBS_ 0

//   </h>
// </h>


// <h> Clock Configuration
//   <h> Clock Control Register Configuration (RCC_CR)
//     <e> PLLON: PLL enable (RCC_CR.24)         
//       <i> Default: PLL Disabled
#define __PLLON_ 1

//       <o.0..3> PLLMUL: PLL Multiplication Factor (RCC_CFGR.18..21)
//         <i> Default: PLLSRC * 2
//                       <0=> PLLSRC * 2
//                       <1=> PLLSRC * 3
//                       <2=> PLLSRC * 4
//                       <3=> PLLSRC * 5
//                       <4=> PLLSRC * 6
//                       <5=> PLLSRC * 7
//                       <6=> PLLSRC * 8
//                       <7=> PLLSRC * 9
//                       <8=> PLLSRC * 10
//                       <9=> PLLSRC * 11
//                       <10=> PLLSRC * 12
//                       <11=> PLLSRC * 13
//                       <12=> PLLSRC * 14
//                       <13=> PLLSRC * 15
//                       <14=> PLLSRC * 16
#define __PLLMUL_ 7

//       <o.0> PLLXTPRE: HSE divider for PLL entry (RCC_CFGR.17)
//         <i> Default: HSE
//                       <0=> HSE
//                       <1=> HSE / 2
#define __PLLXTPRE_ 0

//       <o.0> PLLSRC: PLL entry clock source (RCC_CFGR.16)         
//         <i> Default: HSI/2
//                       <0=> HSI / 2
//                       <1=> HSE (PLLXTPRE output)
#define __PLLSRC_ 1
//     </e>

//     <o.0> CSSON: Clock Security System enable (RCC_CR.19)
//       <i> Default: Clock detector OFF
#define __CSSON_ 0

//     <o.0> HSEBYP: External High Speed clock Bypass (RCC_CR.18)
//       <i> Default: HSE oscillator not bypassed
#define __HSEBYP_ 0

//     <o.0> HSEON: External High Speed clock enable (RCC_CR.16) 
//       <i> Default: HSE oscillator OFF
#define __HSEON_ 1

//     <o.0..4> HSITRIM: Internal High Speed clock trimming (RCC_CR.3..7)  <0-31> */
//       <i> Default: 0                                                           */
#define __HSITRIM_ 16

//     <o.0> HSION: Internal High Speed clock enable (RCC_CR.0)
//       <i> Default: internal 8MHz RC oscillator OFF
#define __HSION_ 0
//   </h>

//   <h> Clock Configuration Register Configuration (RCC_CFGR)
//     <o.0..2> MCO: Microcontroller Clock Output (RCC_CFGR.24..26)  
//       <i> Default: MCO = noClock
//                     <0=> MCO = noClock
//                     <4=> MCO = SYSCLK
//                     <5=> MCO = HSI
//                     <6=> MCO = HSE
//                     <7=> MCO = PLLCLK / 2
#define __MCO_ 0

//     <o.0> USBPRE: USB prescaler (RCC_CFGR.22)
//       <i> Default: USBCLK = PLLCLK / 1.5
//                     <0=> USBCLK = PLLCLK / 1.5
//                     <1=> USBCLK = PLLCLK
#define __USBPRE_ 0

//     <o.0..1> ADCPRE: ADC prescaler (RCC_CFGR.14..15)
//       <i> Default: ADCCLK=PCLK2 / 2
//                     <0=> ADCCLK = PCLK2 / 2
//                     <1=> ADCCLK = PCLK2 / 4
//                     <2=> ADCCLK = PCLK2 / 6
//                     <3=> ADCCLK = PCLK2 / 8
#define __ADCPRE_ 2

//     <o.0..2> PPRE2: APB High speed prescaler (APB2) (RCC_CFGR.11..13)
//       <i> Default: PCLK2 = HCLK
//                     <0=> PCLK2 = HCLK
//                     <4=> PCLK2 = HCLK / 2 
//                     <5=> PCLK2 = HCLK / 4 
//                     <6=> PCLK2 = HCLK / 8 
//                     <7=> PCLK2 = HCLK / 16 
#define __PPRE2_ 0

//     <o.0..2> PPRE1: APB Low speed prescaler (APB1) (RCC_CFGR.8..10) 
//       <i> Default: PCLK1 = HCLK
//                     <0=> PCLK1 = HCLK
//                     <4=> PCLK1 = HCLK / 2 
//                     <5=> PCLK1 = HCLK / 4 
//                     <6=> PCLK1 = HCLK / 8 
//                     <7=> PCLK1 = HCLK / 16 
#define __PPRE1_ 4

//     <o.0..3> HPRE: AHB prescaler (RCC_CFGR.4..7) 
//       <i> Default: HCLK = SYSCLK
//                     <0=> HCLK = SYSCLK
//                     <8=> HCLK = SYSCLK / 2
//                     <9=> HCLK = SYSCLK / 4
//                     <10=> HCLK = SYSCLK / 8
//                     <11=> HCLK = SYSCLK / 16
//                     <12=> HCLK = SYSCLK / 64
//                     <13=> HCLK = SYSCLK / 128
//                     <14=> HCLK = SYSCLK / 256
//                     <15=> HCLK = SYSCLK / 512
#define __HPRE_ 0

//     <o.0..1> SW: System Clock Switch (RCC_CFGR.0..1)
//       <i> Default: SYSCLK = HSE
//                     <0=> SYSCLK = HSI
//                     <1=> SYSCLK = HSE
//                     <2=> SYSCLK = PLLCLK
#define __SW_ 2
//   </h>

//   <o>HSE: External High Speed Clock [Hz] <4000000-16000000>
//   <i> clock value for the used External High Speed Clock (4MHz <= HSE <= 16MHz).
//   <i> Default: 8000000  (8MHz)
#define __HSE 8000000

// </h>

//-------- <<< end of configuration section >>> -----------------


/*----------------------------------------------------------------------------
  Check the settings
 *----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max)     (((val) < (min)) || ((val) > (max)))

/* Embedded Flash Configuration ----------------------------------------------*/
#if (CHECK_RANGE((__LATENCY_), 0, 2))
   #error "LATENCY: Latency (FLASH_ACR.0..2) wrong"
#endif

#if (CHECK_RANGE((__HLFCYA_), 0, 1))
   #error "HLFCYA: Flash Half Cycle Access Enable (FLASH_ACR.3) wrong"
#endif

#if (CHECK_RANGE((__PRFTBE_), 0, 1))
   #error "PRFTBE: Prefetch Buffer Enable (FLASH_ACR.4) wrong"
#endif

#if (CHECK_RANGE((__PRFTBS_), 0, 1))
   #error "PRFTBS: Prefetch Buffer Status Enable (FLASH_ACR.5) wrong"
#endif


/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RANGE((__PLLON_), 0, 1))
   #error "PLLON: PLL enable (RCC_CR.24) wrong"
#endif

#if (CHECK_RANGE((__PLLMUL_), 0, 14))
   #error "PLLMUL: PLL Multiplication Factor (RCC_CFGR.18..21) wrong"
#endif

#if (CHECK_RANGE((__PLLXTPRE_), 0, 1))
   #error "PLLXTPRE: HSE divider for PLL entry (RCC_CFGR.17) wrong"
#endif

#if (CHECK_RANGE((__PLLSRC_), 0, 1))