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📄 main.i

📁 Cortex-m3微控制器软件接口标准 不错的资料
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#line 1 "main.c"



















 


#line 1 "../stm32.h"



















 









 

typedef enum IRQn
{
 
  NonMaskableInt_IRQn             = -14,       
  MemoryManagement_IRQn           = -12,       
  BusFault_IRQn                   = -11,       
  UsageFault_IRQn                 = -10,       
  SVCall_IRQn                     = -5,        
  DebugMonitor_IRQn               = -4,        
  PendSV_IRQn                     = -2,        
  SysTick_IRQn                    = -1,        

 
  WWDG_IRQn                   = 0,         
  PVD_IRQn                    = 1,         
  TAMPER_IRQn                 = 2,         
  RTC_IRQn                    = 3,         
  FLASH_IRQn                  = 4,         
  RCC_IRQn                    = 5,         
  EXTI0_IRQn                  = 6,         
  EXTI1_IRQn                  = 7,         
  EXTI2_IRQn                  = 8,         
  EXTI3_IRQn                  = 9,         
  EXTI4_IRQn                  = 10,        
  DMAChannel1_IRQn            = 11,        
  DMAChannel2_IRQn            = 12,        
  DMAChannel3_IRQn            = 13,        
  DMAChannel4_IRQn            = 14,        
  DMAChannel5_IRQn            = 15,        
  DMAChannel6_IRQn            = 16,        
  DMAChannel7_IRQn            = 17,        
  ADC_IRQn                    = 18,        
  USB_HP_CAN_TX_IRQn          = 19,        
  USB_LP_CAN_RX0_IRQn         = 20,        
  CAN_RX1_IRQn                = 21,        
  CAN_SCE_IRQn                = 22,        
  EXTI9_5_IRQn                = 23,        
  TIM1_BRK_IRQn               = 24,        
  TIM1_UP_IRQn                = 25,        
  TIM1_TRG_COM_IRQn           = 26,        
  TIM1_CC_IRQn                = 27,        
  TIM2_IRQn                   = 28,        
  TIM3_IRQn                   = 29,        
  TIM4_IRQn                   = 30,        
  I2C1_EV_IRQn                = 31,        
  I2C1_ER_IRQn                = 32,        
  I2C2_EV_IRQn                = 33,        
  I2C2_ER_IRQn                = 34,        
  SPI1_IRQn                   = 35,        
  SPI2_IRQn                   = 36,        
  USART1_IRQn                 = 37,        
  USART2_IRQn                 = 38,        
  USART3_IRQn                 = 39,        
  EXTI15_10_IRQn              = 40,        
  RTCAlarm_IRQn               = 41,        
  USBWakeUp_IRQn              = 42         
} IRQn_Type;






 

 





#line 1 "../core_cm3.h"



















 



















































 

 
 
 
 
 
 
 
 


#line 1 "C:\\Keil\\ARM\\RV31\\INC\\stdint.h"
 
 





 









#line 25 "C:\\Keil\\ARM\\RV31\\INC\\stdint.h"







 

     

     
typedef   signed          char int8_t;
typedef   signed short     int int16_t;
typedef   signed           int int32_t;
typedef   signed       __int64 int64_t;

     
typedef unsigned          char uint8_t;
typedef unsigned short     int uint16_t;
typedef unsigned           int uint32_t;
typedef unsigned       __int64 uint64_t;

     

     
     
typedef   signed          char int_least8_t;
typedef   signed short     int int_least16_t;
typedef   signed           int int_least32_t;
typedef   signed       __int64 int_least64_t;

     
typedef unsigned          char uint_least8_t;
typedef unsigned short     int uint_least16_t;
typedef unsigned           int uint_least32_t;
typedef unsigned       __int64 uint_least64_t;

     

     
typedef   signed           int int_fast8_t;
typedef   signed           int int_fast16_t;
typedef   signed           int int_fast32_t;
typedef   signed       __int64 int_fast64_t;

     
typedef unsigned           int uint_fast8_t;
typedef unsigned           int uint_fast16_t;
typedef unsigned           int uint_fast32_t;
typedef unsigned       __int64 uint_fast64_t;

     
typedef   signed           int intptr_t;
typedef unsigned           int uintptr_t;

     
typedef   signed       __int64 intmax_t;
typedef unsigned       __int64 uintmax_t;




     

     





     





     





     

     





     





     





     

     





     





     





     

     


     


     


     

     


     


     


     

     



     



     


     
    
 



#line 196 "C:\\Keil\\ARM\\RV31\\INC\\stdint.h"

     







     










     











#line 260 "C:\\Keil\\ARM\\RV31\\INC\\stdint.h"



 


#line 85 "../core_cm3.h"

















 









 


 





 






 
typedef struct
{
  volatile uint32_t ISER[8];                       
       uint32_t RESERVED0[24];
  volatile uint32_t ICER[8];                       
  volatile uint32_t RSERVED1[24];
  volatile uint32_t ISPR[8];                       
       uint32_t RESERVED2[24];
  volatile uint32_t ICPR[8];                       
       uint32_t RESERVED3[24];
  volatile uint32_t IABR[8];                       
       uint32_t RESERVED4[56];
  volatile uint8_t  IP[240];                       
       uint32_t RESERVED5[644];
  volatile  uint32_t STIR;                          
}  NVIC_Type;


 
typedef struct
{
  volatile const  uint32_t CPUID;                         
  volatile uint32_t ICSR;                          
  volatile uint32_t VTOR;                          
  volatile uint32_t AIRCR;                         
  volatile uint32_t SCR;                           
  volatile uint32_t CCR;                           
  volatile uint8_t  SHP[12];                       
  volatile uint32_t SHCSR;                         
  volatile uint32_t CFSR;                          
  volatile uint32_t HFSR;                          
  volatile uint32_t DFSR;                          
  volatile uint32_t MMFAR;                         
  volatile uint32_t BFAR;                          
  volatile uint32_t AFSR;                          
  volatile const  uint32_t PFR[2];                        
  volatile const  uint32_t DFR;                           
  volatile const  uint32_t ADR;                           
  volatile const  uint32_t MMFR[4];                       
  volatile const  uint32_t ISAR[5];                       
} SCB_Type;



 
typedef struct
{
  volatile uint32_t CTRL;                          
  volatile uint32_t LOAD;                          
  volatile uint32_t VAL;                           
  volatile const  uint32_t CALIB;                         
} SysTick_Type;



 
typedef struct
{
  volatile  union  
  {
    volatile  uint8_t    u8;                        
    volatile  uint16_t   u16;                       
    volatile  uint32_t   u32;                       
  }  PORT [32];                                
       uint32_t RESERVED0[864];
  volatile uint32_t TER;                           
       uint32_t RESERVED1[15];
  volatile uint32_t TPR;                           
       uint32_t RESERVED2[15];
  volatile uint32_t TCR;                           
       uint32_t RESERVED3[29];
  volatile uint32_t IWR;                           
  volatile uint32_t IRR;                           
  volatile uint32_t IMCR;                          
       uint32_t RESERVED4[43];
  volatile uint32_t LAR;                           
  volatile uint32_t LSR;                           
       uint32_t RESERVED5[6];
  volatile const  uint32_t PID4;                          
  volatile const  uint32_t PID5;
  volatile const  uint32_t PID6;
  volatile const  uint32_t PID7;
  volatile const  uint32_t PID0;
  volatile const  uint32_t PID1;
  volatile const  uint32_t PID2;
  volatile const  uint32_t PID3;
  volatile const  uint32_t CID0;
  volatile const  uint32_t CID1;
  volatile const  uint32_t CID2;
  volatile const  uint32_t CID3;
} ITM_Type;


 
typedef struct
{
       uint32_t RESERVED0;
  volatile const  uint32_t ICTR;                          



       uint32_t RESERVED1;

} InterruptType_Type;


 
#line 252 "../core_cm3.h"


 
typedef struct
{
  volatile uint32_t DHCSR;    
  volatile  uint32_t DCRSR;    
  volatile uint32_t DCRDR;    
  volatile uint32_t DEMCR;    
} CoreDebug_Type;


 
#line 271 "../core_cm3.h"

#line 278 "../core_cm3.h"










 


#line 299 "../core_cm3.h"

#line 306 "../core_cm3.h"


 


 




#line 331 "../core_cm3.h"






   
   
   
   



#line 459 "../core_cm3.h"








 
extern uint32_t __get_PSP(void);









 
extern void __set_PSP(uint32_t topOfProcStack);









 
extern uint32_t __get_MSP(void);









 
extern void __set_MSP(uint32_t topOfMainStack);








 
extern uint32_t __get_BASEPRI(void);








 
extern void __set_BASEPRI(uint32_t basePri);









 
extern uint32_t __get_PRIMASK(void);








 
extern void __set_PRIMASK(uint32_t priMask);








 
extern uint32_t __get_FAULTMASK(void);








 
extern void __set_FAULTMASK(uint32_t faultMask);








 
extern uint32_t __get_CONTROL(void);








 
extern void __set_CONTROL(uint32_t control);









 
extern uint32_t __REV16(uint16_t value);









 
extern int32_t __REVSH(int16_t value);









#line 1043 "../core_cm3.h"



 










 
static __inline void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
{
  uint32_t reg_value=0;
  
  reg_value  = ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR;                                                       
  reg_value &= ~((0xffffU << 16) | (0x0f << 8));                                 
  reg_value  = ((reg_value | (0x5FA << 16) | (priority_grouping << 8)));    
  ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR = reg_value;
}







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