system_stm32.txt

Cortex-m3微控制器软件接口标准 不错的资料

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 934] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\obj\system_stm32.o --depend=.\obj\system_stm32.d --device=DARMSTM --apcs=interwork -O0 -I../ -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\obj\system_stm32.crf ..\system_stm32.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  SystemInit PROC
;;;417    {
;;;418      FLASH->ACR = __EFI_ACR_Val;                        /* set access control register        */
000000  2012              MOVS     r0,#0x12
000002  490e              LDR      r1,|L1.60|
000004  6008              STR      r0,[r1,#0]
;;;419    
;;;420      RCC->CFGR = __RCC_CFGR_VAL;                        /* set clock configuration register   */
000006  480e              LDR      r0,|L1.64|
000008  490e              LDR      r1,|L1.68|
00000a  6048              STR      r0,[r1,#4]
;;;421      RCC->CR   = __RCC_CR_VAL;                          /* set clock control register         */
00000c  480e              LDR      r0,|L1.72|
00000e  6008              STR      r0,[r1,#0]
;;;422    
;;;423      if (__RCC_CR_VAL & RCC_CR_HSION) {                 /* if HSI enabled                     */
000010  bf00              NOP      
;;;424        while ((RCC->CR & RCC_CR_HSIRDY) == 0);          /* Wait for HSIRDY = 1 (HSI is ready) */
;;;425      }
;;;426    
;;;427      if (__RCC_CR_VAL & RCC_CR_HSEON) {                 /* if HSE enabled                     */
;;;428        while ((RCC->CR & RCC_CR_HSERDY) == 0);          /* Wait for HSERDY = 1 (HSE is ready) */
000012  bf00              NOP      
                  |L1.20|
000014  480b              LDR      r0,|L1.68|
000016  6800              LDR      r0,[r0,#0]
000018  f410f410          TST      r0,#0x20000
00001c  d0fa              BEQ      |L1.20|
;;;429      }
;;;430    
;;;431      if (__RCC_CR_VAL & RCC_CR_PLLON) {                 /* if PLL enabled                     */
;;;432        while ((RCC->CR & RCC_CR_PLLRDY) == 0);          /* Wait for PLLRDY = 1 (PLL is ready) */
00001e  bf00              NOP      
                  |L1.32|
000020  4808              LDR      r0,|L1.68|
000022  6800              LDR      r0,[r0,#0]
000024  f010f010          TST      r0,#0x2000000
000028  d0fa              BEQ      |L1.32|
;;;433      }
;;;434    
;;;435      /* Wait till SYSCLK is stabilized (depending on selected clock) */
;;;436      while ((RCC->CFGR & RCC_CFGR_SWS) != ((__RCC_CFGR_VAL<<2) & RCC_CFGR_SWS));
00002a  bf00              NOP      
                  |L1.44|
00002c  4805              LDR      r0,|L1.68|
00002e  6840              LDR      r0,[r0,#4]
000030  f000f000          AND      r0,r0,#0xc
000034  2808              CMP      r0,#8
000036  d1f9              BNE      |L1.44|
;;;437    }
000038  4770              BX       lr
;;;438    
                          ENDP

00003a  0000              DCW      0x0000
                  |L1.60|
00003c  40022000          DCD      0x40022000
                  |L1.64|
000040  001d8402          DCD      0x001d8402
                  |L1.68|
000044  40021000          DCD      0x40021000
                  |L1.72|
000048  01010080          DCD      0x01010080

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                  SystemFrequency
000000  044aa200          DCD      0x044aa200
                  SystemFrequency_SysClk
000004  044aa200          DCD      0x044aa200
                  SystemFrequency_AHBClk
000008  044aa200          DCD      0x044aa200
                  SystemFrequency_APB1Clk
00000c  02255100          DCD      0x02255100
                  SystemFrequency_APB2Clk
000010  044aa200          DCD      0x044aa200