stm32.h

Cortex-m3微控制器软件接口标准 不错的资料

/******************************************************************************
 * @file:    stm32.h
 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
 * @version: V1.0
 * @date:    12. Nov. 2008
 *----------------------------------------------------------------------------
 *
 * Copyright (C) 2008 ARM Limited. All rights reserved.
 *
 * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
 * processor based microcontrollers.  This file can be freely distributed 
 * within development tools that are supporting such ARM based processors. 
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/


#ifndef __STM32_H__
#define __STM32_H__

/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
 */

typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions Numbers **********************************************************/
  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */

/******  STM32 specific Interrupt Numbers ****************************************************************/
  WWDG_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
  PVD_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
  TAMPER_IRQn                 = 2,        /*!< Tamper Interrupt                                      */
  RTC_IRQn                    = 3,        /*!< RTC global Interrupt                                  */
  FLASH_IRQn                  = 4,        /*!< FLASH global Interrupt                                */
  RCC_IRQn                    = 5,        /*!< RCC global Interrupt                                  */
  EXTI0_IRQn                  = 6,        /*!< EXTI Line0 Interrupt                                  */
  EXTI1_IRQn                  = 7,        /*!< EXTI Line1 Interrupt                                  */
  EXTI2_IRQn                  = 8,        /*!< EXTI Line2 Interrupt                                  */
  EXTI3_IRQn                  = 9,        /*!< EXTI Line3 Interrupt                                  */
  EXTI4_IRQn                  = 10,       /*!< EXTI Line4 Interrupt                                  */
  DMAChannel1_IRQn            = 11,       /*!< DMA Channel 1 global Interrupt                        */
  DMAChannel2_IRQn            = 12,       /*!< DMA Channel 2 global Interrupt                        */
  DMAChannel3_IRQn            = 13,       /*!< DMA Channel 3 global Interrupt                        */
  DMAChannel4_IRQn            = 14,       /*!< DMA Channel 4 global Interrupt                        */
  DMAChannel5_IRQn            = 15,       /*!< DMA Channel 5 global Interrupt                        */
  DMAChannel6_IRQn            = 16,       /*!< DMA Channel 6 global Interrupt                        */
  DMAChannel7_IRQn            = 17,       /*!< DMA Channel 7 global Interrupt                        */
  ADC_IRQn                    = 18,       /*!< ADC global Interrupt                                  */
  USB_HP_CAN_TX_IRQn          = 19,       /*!< USB High Priority or CAN TX Interrupts                */
  USB_LP_CAN_RX0_IRQn         = 20,       /*!< USB Low Priority or CAN RX0 Interrupts                */
  CAN_RX1_IRQn                = 21,       /*!< CAN RX1 Interrupt                                     */
  CAN_SCE_IRQn                = 22,       /*!< CAN SCE Interrupt                                     */
  EXTI9_5_IRQn                = 23,       /*!< External Line[9:5] Interrupts                         */
  TIM1_BRK_IRQn               = 24,       /*!< TIM1 Break Interrupt                                  */
  TIM1_UP_IRQn                = 25,       /*!< TIM1 Update Interrupt                                 */
  TIM1_TRG_COM_IRQn           = 26,       /*!< TIM1 Trigger and Commutation Interrupt                */
  TIM1_CC_IRQn                = 27,       /*!< TIM1 Capture Compare Interrupt                        */
  TIM2_IRQn                   = 28,       /*!< TIM2 global Interrupt                                 */
  TIM3_IRQn                   = 29,       /*!< TIM3 global Interrupt                                 */
  TIM4_IRQn                   = 30,       /*!< TIM4 global Interrupt                                 */
  I2C1_EV_IRQn                = 31,       /*!< I2C1 Event Interrupt                                  */
  I2C1_ER_IRQn                = 32,       /*!< I2C1 Error Interrupt                                  */
  I2C2_EV_IRQn                = 33,       /*!< I2C2 Event Interrupt                                  */
  I2C2_ER_IRQn                = 34,       /*!< I2C2 Error Interrupt                                  */
  SPI1_IRQn                   = 35,       /*!< SPI1 global Interrupt                                 */
  SPI2_IRQn                   = 36,       /*!< SPI2 global Interrupt                                 */
  USART1_IRQn                 = 37,       /*!< USART1 global Interrupt                               */
  USART2_IRQn                 = 38,       /*!< USART2 global Interrupt                               */
  USART3_IRQn                 = 39,       /*!< USART3 global Interrupt                               */
  EXTI15_10_IRQn              = 40,       /*!< External Line[15:10] Interrupts                       */
  RTCAlarm_IRQn               = 41,       /*!< RTC Alarm through EXTI Line Interrupt                 */
  USBWakeUp_IRQn              = 42        /*!< USB WakeUp from suspend through EXTI Line Interrupt   */
} IRQn_Type;


/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT             0           /*!< STM32 does not provide a MPU present or not  */
#define __NVIC_PRIO_BITS          4           /*!< STM32 uses 4 Bits for the Priority Levels    */
#define __Vendor_SysTickConfig    0           /*!< Set to 1 if different SysTick Config is used   */


#include "core_cm3.h"                         /* Cortex-M3 processor and core peripherals     */
#include "system_stm32.h"                     /* STM32 System                                 */



/**
 * Initialize the system clock
 *
 * @param  none
 * @return none
 *
 * @brief  Setup the microcontroller system
 *         Initialize the PLL and update th SystemFrequency variable
 */
extern                   void SystemInit     (void);


/******************************************************************************/
/*                Device Specific Peripheral registers structures             */
/******************************************************************************/

/*------------------------ Analog to Digital Converter -----------------------*/
typedef struct
{
  __IO uint32_t SR;
  __IO uint32_t CR1;
  __IO uint32_t CR2;
  __IO uint32_t SMPR1;
  __IO uint32_t SMPR2;
  __IO uint32_t JOFR1;
  __IO uint32_t JOFR2;
  __IO uint32_t JOFR3;
  __IO uint32_t JOFR4;
  __IO uint32_t HTR;
  __IO uint32_t LTR;
  __IO uint32_t SQR1;
  __IO uint32_t SQR2;
  __IO uint32_t SQR3;
  __IO uint32_t JSQR;
  __IO uint32_t JDR1;
  __IO uint32_t JDR2;
  __IO uint32_t JDR3;
  __IO uint32_t JDR4;
  __IO uint32_t DR;
} ADC_TypeDef;

/*------------------------ Backup Registers ----------------------------------*/
typedef struct
{
       uint32_t RESERVED0;
  __IO uint16_t DR1;
       uint16_t RESERVED1;
  __IO uint16_t DR2;
       uint16_t RESERVED2;
  __IO uint16_t DR3;
       uint16_t RESERVED3;
  __IO uint16_t DR4;
       uint16_t RESERVED4;
  __IO uint16_t DR5;
       uint16_t RESERVED5;
  __IO uint16_t DR6;
       uint16_t RESERVED6;
  __IO uint16_t DR7;
       uint16_t RESERVED7;
  __IO uint16_t DR8;
       uint16_t RESERVED8;
  __IO uint16_t DR9;
       uint16_t RESERVED9;
  __IO uint16_t DR10;
       uint16_t RESERVED10;
  __IO uint16_t RTCCR;
       uint16_t RESERVED11;
  __IO uint16_t CR;
       uint16_t RESERVED12;
  __IO uint16_t CSR;
       uint16_t RESERVED13;
} BKP_TypeDef;

/*------------------------ Controller Area Network ---------------------------*/
typedef struct
{
  __IO uint32_t TIR;
  __IO uint32_t TDTR;
  __IO uint32_t TDLR;
  __IO uint32_t TDHR;
} CAN_TxMailBox_TypeDef;

typedef struct
{
  __IO uint32_t RIR;
  __IO uint32_t RDTR;
  __IO uint32_t RDLR;
  __IO uint32_t RDHR;
} CAN_FIFOMailBox_TypeDef;

typedef struct
{
  __IO uint32_t FR0;
  __IO uint32_t FR1;
} CAN_FilterRegister_TypeDef;

typedef struct
{
  __IO uint32_t MCR;
  __IO uint32_t MSR;
  __IO uint32_t TSR;
  __IO uint32_t RF0R;
  __IO uint32_t RF1R;
  __IO uint32_t IER;
  __IO uint32_t ESR;
  __IO uint32_t BTR;
       uint32_t RESERVED0[88];
  CAN_TxMailBox_TypeDef sTxMailBox[3];
  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
       uint32_t RESERVED1[12];
  __IO uint32_t FMR;
  __IO uint32_t FM0R;
       uint32_t RESERVED2[1];
  __IO uint32_t FS0R;
       uint32_t RESERVED3[1];
  __IO uint32_t FFA0R;
       uint32_t RESERVED4[1];
  __IO uint32_t FA0R;
       uint32_t RESERVED5[8];
  CAN_FilterRegister_TypeDef sFilterRegister[14];
} CAN_TypeDef;

/*------------------------ DMA Controller ------------------------------------*/
typedef struct
{
  __IO uint32_t CCR;
  __IO uint32_t CNDTR;
  __IO uint32_t CPAR;
  __IO uint32_t CMAR;
} DMA_Channel_TypeDef;

typedef struct
{
  __IO uint32_t ISR;
  __IO uint32_t IFCR;
} DMA_TypeDef;

/*------------------------ External Interrupt/Event Controller ---------------*/
typedef struct
{
  __IO uint32_t IMR;
  __IO uint32_t EMR;
  __IO uint32_t RTSR;
  __IO uint32_t FTSR;
  __IO uint32_t SWIER;
  __IO uint32_t PR;
} EXTI_TypeDef;

/*------------------------ FLASH and Option Bytes Registers ------------------*/
typedef struct
{
  __IO uint32_t ACR;
  __IO uint32_t KEYR;
  __IO uint32_t OPTKEYR;
  __IO uint32_t SR;
  __IO uint32_t CR;
  __IO uint32_t AR;
  __IO uint32_t RESERVED;
  __IO uint32_t OBR;
  __IO uint32_t WRPR;
} FLASH_TypeDef;

typedef struct
{
  __IO uint16_t RDP;
  __IO uint16_t USER;
  __IO uint16_t Data0;
  __IO uint16_t Data1;
  __IO uint16_t WRP0;
  __IO uint16_t WRP1;
  __IO uint16_t WRP2;
  __IO uint16_t WRP3;
} OB_TypeDef;

/*------------------------ General Purpose and Alternate Function IO ---------*/
typedef struct
{
  __IO uint32_t CRL;
  __IO uint32_t CRH;
  __IO uint32_t IDR;
  __IO uint32_t ODR;
  __IO uint32_t BSRR;
  __IO uint32_t BRR;
  __IO uint32_t LCKR;
} GPIO_TypeDef;

typedef struct
{
  __IO uint32_t EVCR;
  __IO uint32_t MAPR;
  __IO uint32_t EXTICR[4];
} AFIO_TypeDef;

/*------------------------ Inter-integrated Circuit Interface ----------------*/
typedef struct
{
  __IO uint16_t CR1;
       uint16_t RESERVED0;
  __IO uint16_t CR2;
       uint16_t RESERVED1;
  __IO uint16_t OAR1;
       uint16_t RESERVED2;
  __IO uint16_t OAR2;
       uint16_t RESERVED3;
  __IO uint16_t DR;