ar5416reg.h

最新之atheros芯片driver source code, 基于linux操作系统,內含atheros芯片HAL全部代码

	(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \
	 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \
	 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \
	 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \
	 AR_INTR_SYNC_MAC_SLEEP_ACCESS)

/* RTC registers */
#define	AR_RTC_RC_M		0x00000003
#define	AR_RTC_RC_MAC_WARM	0x00000001
#define	AR_RTC_RC_MAC_COLD	0x00000002
#define	AR_RTC_PLL_DIV		0x0000001f
#define	AR_RTC_PLL_DIV_S	0
#define	AR_RTC_PLL_DIV2		0x00000020
#define	AR_RTC_PLL_REFDIV_5	0x000000c0

#define	AR_RTC_SOWL_PLL_DIV		0x000003ff
#define	AR_RTC_SOWL_PLL_DIV_S		0
#define	AR_RTC_SOWL_PLL_REFDIV		0x00003C00
#define	AR_RTC_SOWL_PLL_REFDIV_S	10
#define	AR_RTC_SOWL_PLL_CLKSEL		0x0000C000
#define	AR_RTC_SOWL_PLL_CLKSEL_S	14

#define	AR_RTC_RESET_EN		0x00000001	/* Reset RTC bit */

#define	AR_RTC_PM_STATUS_M	0x0000000f	/* Pwr Mgmt Status */
#define	AR_RTC_STATUS_M		0x0000003f	/* RTC Status */
#define	AR_RTC_STATUS_SHUTDOWN	0x00000001
#define	AR_RTC_STATUS_ON	0x00000002
#define	AR_RTC_STATUS_SLEEP	0x00000004
#define	AR_RTC_STATUS_WAKEUP	0x00000008
#define	AR_RTC_STATUS_COLDRESET	0x00000010	/* Not currently used */
#define	AR_RTC_STATUS_PLLCHANGE	0x00000020	/* Not currently used */

#define	AR_RTC_SLEEP_DERIVED_CLK	0x2

#define	AR_RTC_FORCE_WAKE_EN	0x00000001	/* enable force wake */
#define	AR_RTC_FORCE_WAKE_ON_INT 0x00000002	/* auto-wake on MAC interrupt */

#define	AR_RTC_PLL_CLKSEL	0x00000300
#define	AR_RTC_PLL_CLKSEL_S	8

/* AR9280: rf long shift registers */
#define	AR_AN_RF2G1_CH0_OB      0x03800000
#define	AR_AN_RF2G1_CH0_OB_S    23
#define	AR_AN_RF2G1_CH0_DB      0x1C000000
#define	AR_AN_RF2G1_CH0_DB_S    26

#define	AR_AN_RF5G1_CH0_OB5     0x00070000
#define	AR_AN_RF5G1_CH0_OB5_S   16
#define	AR_AN_RF5G1_CH0_DB5     0x00380000
#define	AR_AN_RF5G1_CH0_DB5_S   19

#define	AR_AN_RF2G1_CH1_OB      0x03800000
#define	AR_AN_RF2G1_CH1_OB_S    23
#define	AR_AN_RF2G1_CH1_DB      0x1C000000
#define	AR_AN_RF2G1_CH1_DB_S    26

#define	AR_AN_RF5G1_CH1_OB5     0x00070000
#define	AR_AN_RF5G1_CH1_OB5_S   16
#define	AR_AN_RF5G1_CH1_DB5     0x00380000
#define	AR_AN_RF5G1_CH1_DB5_S   19

#define	AR_AN_TOP2_XPABIAS_LVL      0xC0000000
#define	AR_AN_TOP2_XPABIAS_LVL_S    30
#define	AR_AN_TOP2_LOCALBIAS        0x00200000
#define	AR_AN_TOP2_LOCALBIAS_S      21
#define	AR_AN_TOP2_PWDCLKIND        0x00400000
#define	AR_AN_TOP2_PWDCLKIND_S      22

#define	AR_AN_SYNTH9_REFDIVA    0xf8000000
#define	AR_AN_SYNTH9_REFDIVA_S  27

/* AR9285 Analog registers */
#define	AR9285_AN_RF2G3_OB_0    0x00E00000
#define	AR9285_AN_RF2G3_OB_0_S    21
#define	AR9285_AN_RF2G3_OB_1    0x001C0000
#define	AR9285_AN_RF2G3_OB_1_S    18
#define	AR9285_AN_RF2G3_OB_2    0x00038000
#define	AR9285_AN_RF2G3_OB_2_S    15
#define	AR9285_AN_RF2G3_OB_3    0x00007000
#define	AR9285_AN_RF2G3_OB_3_S    12
#define	AR9285_AN_RF2G3_OB_4    0x00000E00
#define	AR9285_AN_RF2G3_OB_4_S    9

#define	AR9285_AN_RF2G3_DB1_0    0x000001C0
#define	AR9285_AN_RF2G3_DB1_0_S    6
#define	AR9285_AN_RF2G3_DB1_1    0x00000038
#define	AR9285_AN_RF2G3_DB1_1_S    3
#define	AR9285_AN_RF2G3_DB1_2    0x00000007
#define	AR9285_AN_RF2G3_DB1_2_S    0
#define	AR9285_AN_RF2G4         0x782C
#define	AR9285_AN_RF2G4_DB1_3    0xE0000000
#define	AR9285_AN_RF2G4_DB1_3_S    29
#define	AR9285_AN_RF2G4_DB1_4    0x1C000000
#define	AR9285_AN_RF2G4_DB1_4_S    26

#define	AR9285_AN_RF2G4_DB2_0    0x03800000
#define	AR9285_AN_RF2G4_DB2_0_S    23
#define	AR9285_AN_RF2G4_DB2_1    0x00700000
#define	AR9285_AN_RF2G4_DB2_1_S    20
#define	AR9285_AN_RF2G4_DB2_2    0x000E0000
#define	AR9285_AN_RF2G4_DB2_2_S    17
#define	AR9285_AN_RF2G4_DB2_3    0x0001C000
#define	AR9285_AN_RF2G4_DB2_3_S    14
#define	AR9285_AN_RF2G4_DB2_4    0x00003800
#define	AR9285_AN_RF2G4_DB2_4_S    11

#define	AR9285_AN_TOP3_XPABIAS_LVL      0x0000000C
#define	AR9285_AN_TOP3_XPABIAS_LVL_S    2

/* Sleep control */
#define	AR5416_SLEEP1_CAB_TIMEOUT	0xFFE00000	/* Cab timeout (TU) */
#define	AR5416_SLEEP1_CAB_TIMEOUT_S	22

#define	AR5416_SLEEP2_BEACON_TIMEOUT	0xFFE00000	/* Beacon timeout (TU)*/
#define	AR5416_SLEEP2_BEACON_TIMEOUT_S	22

/* Sleep Registers */
#define	AR_SLP32_HALFCLK_LATENCY      0x000FFFFF	/* rising <-> falling edge */
#define	AR_SLP32_ENA		0x00100000
#define	AR_SLP32_TSF_WRITE_STATUS      0x00200000	/* tsf update in progress */

#define	AR_SLP32_WAKE_XTL_TIME	0x0000FFFF	/* time to wake crystal */

#define	AR_SLP32_TST_INC	0x000FFFFF

#define	AR_SLP_MIB_CLEAR	0x00000001	/* clear pending */
#define	AR_SLP_MIB_PENDING	0x00000002	/* clear counters */

#define	AR_TIMER_MODE_TBTT		0x00000001
#define	AR_TIMER_MODE_DBA		0x00000002
#define	AR_TIMER_MODE_SWBA		0x00000004
#define	AR_TIMER_MODE_HCF		0x00000008
#define	AR_TIMER_MODE_TIM		0x00000010
#define	AR_TIMER_MODE_DTIM		0x00000020
#define	AR_TIMER_MODE_QUIET		0x00000040
#define	AR_TIMER_MODE_NDP		0x00000080
#define	AR_TIMER_MODE_OVERFLOW_INDEX	0x00000700
#define	AR_TIMER_MODE_OVERFLOW_INDEX_S	8
#define	AR_TIMER_MODE_THRESH		0xFFFFF000
#define	AR_TIMER_MODE_THRESH_S		12

/* PCU Misc modes */
#define	AR_PCU_FORCE_BSSID_MATCH	0x00000001 /* force bssid to match */
#define	AR_PCU_MIC_NEW_LOC_ENA		0x00000004 /* tx/rx mic keys together */
#define	AR_PCU_TX_ADD_TSF		0x00000008 /* add tx_tsf + int_tsf */
#define	AR_PCU_CCK_SIFS_MODE		0x00000010 /* assume 11b sifs */
#define	AR_PCU_RX_ANT_UPDT		0x00000800 /* KC_RX_ANT_UPDATE */
#define	AR_PCU_TXOP_TBTT_LIMIT_ENA	0x00001000 /* enforce txop / tbtt */
#define	AR_PCU_MISS_BCN_IN_SLEEP	0x00004000 /* count bmiss's when sleeping */
#define	AR_PCU_BUG_12306_FIX_ENA	0x00020000 /* use rx_clear to count sifs */
#define	AR_PCU_FORCE_QUIET_COLL		0x00040000 /* kill xmit for channel change */
#define	AR_PCU_TBTT_PROTECT		0x00200000 /* no xmit upto tbtt+20 uS */
#define	AR_PCU_CLEAR_VMF		0x01000000 /* clear vmf mode (fast cc)*/
#define	AR_PCU_CLEAR_BA_VALID		0x04000000 /* clear ba state */

/* GPIO Interrupt */
#define	AR_INTR_GPIO		0x3FF00000	/* gpio interrupted */
#define	AR_INTR_GPIO_S		20

#define	AR_GPIO_OUT_CTRL	0x000003FF	/* 0 = out, 1 = in */
#define	AR_GPIO_OUT_VAL		0x000FFC00
#define	AR_GPIO_OUT_VAL_S	10
#define	AR_GPIO_INTR_CTRL	0x3FF00000
#define	AR_GPIO_INTR_CTRL_S	20

#define	AR_2040_JOINED_RX_CLEAR	0x00000001	/* use ctl + ext rx_clear for cca */

#define	AR_PCU_TXBUF_CTRL_SIZE_MASK	0x7FF
#define	AR_PCU_TXBUF_CTRL_USABLE_SIZE	0x700

/* Eeprom defines */
#define	AR_EEPROM_STATUS_DATA_VAL           0x0000ffff
#define	AR_EEPROM_STATUS_DATA_VAL_S         0
#define	AR_EEPROM_STATUS_DATA_BUSY          0x00010000
#define	AR_EEPROM_STATUS_DATA_BUSY_ACCESS   0x00020000
#define	AR_EEPROM_STATUS_DATA_PROT_ACCESS   0x00040000
#define	AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000

#define	AR_SREV_REVISION_OWL_10		0x08
#define	AR_SREV_REVISION_OWL_20		0x09
#define	AR_SREV_REVISION_OWL_22		0x0a

#define	AR_RAD5133_SREV_MAJOR		0xc0	/* Fowl: 2+5G/3x3 */
#define	AR_RAD2133_SREV_MAJOR		0xd0	/* Fowl: 2G/3x3   */
#define	AR_RAD5122_SREV_MAJOR		0xe0	/* Fowl: 5G/2x2   */
#define	AR_RAD2122_SREV_MAJOR		0xf0	/* Fowl: 2+5G/2x2 */

/* Test macro for owl 1.0 */
#define	IS_5416V1(_ah)	((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10)  
#define	IS_5416V2(_ah)	((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20)
#define	IS_5416V2_2(_ah)	((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) 

/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */
#define	AR_XSREV_ID		0xFFFFFFFF	/* Chip ID */
#define	AR_XSREV_ID_S		0
#define	AR_XSREV_VERSION	0xFFFC0000	/* Chip version */
#define	AR_XSREV_VERSION_S	18
#define	AR_XSREV_TYPE		0x0003F000	/* Chip type */
#define	AR_XSREV_TYPE_S		12
#define	AR_XSREV_TYPE_CHAIN	0x00001000	/* Chain Mode (1:3 chains,
						 * 0:2 chains) */
#define	AR_XSREV_TYPE_HOST_MODE 0x00002000	/* Host Mode (1:PCI, 0:PCIe) */
#define	AR_XSREV_REVISION	0x00000F00
#define	AR_XSREV_REVISION_S	8

#define	AR_XSREV_VERSION_OWL_PCI	0x0D
#define	AR_XSREV_VERSION_OWL_PCIE	0x0C
#define	AR_XSREV_REVISION_OWL_10	0	/* Owl 1.0 */
#define	AR_XSREV_REVISION_OWL_20	1	/* Owl 2.0/2.1 */
#define	AR_XSREV_REVISION_OWL_22	2	/* Owl 2.2 */
#define	AR_XSREV_VERSION_SOWL		0x40
#define	AR_XSREV_REVISION_SOWL_10	0	/* Sowl 1.0 */
#define	AR_XSREV_REVISION_SOWL_11	1	/* Sowl 1.1 */
#define	AR_XSREV_VERSION_MERLIN		0x80	/* Merlin Version */
#define	AR_XSREV_REVISION_MERLIN_10	0	/* Merlin 1.0 */
#define	AR_XSREV_REVISION_MERLIN_20	1	/* Merlin 2.0 */
#define	AR_XSREV_REVISION_MERLIN_21	2	/* Merlin 2.1 */
#define	AR_XSREV_VERSION_KITE		0xC0	/* Kite Version */
#define	AR_XSREV_REVISION_KITE_10	0	/* Kite 1.0 */

#define	AR_SREV_OWL_20_OR_LATER(_ah) \
	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20)
#define	AR_SREV_OWL_22_OR_LATER(_ah) \
	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22)

#define	AR_SREV_SOWL(_ah) \
	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL)
#define	AR_SREV_SOWL_10_OR_LATER(_ah) \
	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL)
#define	AR_SREV_SOWL_11(_ah) \
	(AR_SREV_SOWL(_ah) && \
	 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11)

#define	AR_SREV_MERLIN(_ah) \
	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN)
#define	AR_SREV_MERLIN_10_OR_LATER(_ah)	\
	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
#define	AR_SREV_MERLIN_20(_ah) \
	(AR_SREV_MERLIN(_ah) && \
	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)
#define	AR_SREV_MERLIN_20_OR_LATER(_ah) \
	(AR_SREV_MERLIN_20(_ah) || \
	 AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)

#define	AR_SREV_KITE(_ah) \
	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)
#define	AR_SREV_KITE_10_OR_LATER(_ah) \
	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE)
#endif /* _DEV_ATH_AR5416REG_H */